An all digital timing loop is employed in a hard disk drive read channel for improved timing performance. Synchronizing the read channel to a sinewave preamble pattern at the beginning of a servo or data read operation is accomplished by first determining an accurate initial estimate of phase angle, and loading that phase value into the digital phase lock loop phase interpolator without having to halt and restart the sample clock. The timing loop synchronizes to the preamble input pattern very quickly so that timing overhead is reduced. The initial phase estimate is formed by accumulating even and odd ADC samples over a selected integration period, and using those values to access an arctan lookup table. Since ratios of even and odd ADC samples are used, gain variations and other analog tolerance issues are avoided.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An improved method of fast timing acquisition of a preamble pattern input signal in a magnetic read channel, comprising the steps of: providing a phase-lock loop circuit having a digital VCO that provides as its output a sampling clock signal arranged for sampling the input signal; at the beginning of a read operation, providing a reference clock signal to the digital VCO and sampling the input signal in response to the reference clock signal; estimating an initial phase of the input signal based on said sampling step, including digitally integrating an even series of samples of the input signal to form an estimated cosine value; digitally integrating an odd series of samples of the input signal to form an estimated sine value; and then determining the initial phase estimate by applying an arctangent function to the estimated sine and cosine values; adjusting a phase of the digital VCO, and thereby adjusting a phase of the sampling clock signal, responsive to the estimated initial phase of the input signal; and then commencing normal operation of the phase-lock loop using the adjusted sampling clock signal, rather than the reference clock signal, for sampling the input signal.
2. A method according to claim 1 wherein the digital VCO includes an integrator circuit for estimating the phase of the input signal and a phase interpolator circuit to effect said adjusting the phase of the sampling clock signal.
3. A method according to claim 2 wherein said estimating the initial phase of the input signal includes forming a digital value indicative of the initial phase of the input signal, and said adjusting the phase of the digital VCO includes providing said digital value to the phase interpolator circuit to adjust the phase of the sampling signal by an amount responsive to the digital value.
4. A method according to claim 1 wherein said digitally integrating steps include digitally summing the corresponding series of input signal sample values over a selected integration period.
5. A method according to claim 4 wherein the integration period is programmably selectable.
6. A method according to claim 1 wherein said applying the arctangent function includes providing a look-up table of arctangent values addressable according to the estimated sine and cosine input values.
7. A method according to claim 6 wherein the look-up table comprises a half-size table comprising only a selected one of only non-negative cosine or sine entries.
8. A digital timing loop circuit for use in a magnetic read channel comprising: an analog to digital converter means for sampling an analog input signal responsive to a sampling clock signal; a memory means for storing alternate samples from the analog to digital converter means so as to form even and odd streams of ADC samples; means for forming an initial phase estimate value responsive to the even and odd ADC sample streams, including a first digital accumulator for accumulating the even stream of ADC values and a second digital accumulator for accumulating the odd stream of ADC values; and digital phase interpolating means for shifting the sampling clock signal responsive to the initial phase estimate value at the beginning of the read operation so as to bring the sampling clock signal into alignment with the said analog input signal without halting the sampling clock.
9. A digital timing loop circuit according to claim 8 and further comprising means for dividing the accumulated even and odd ADC values in accordance with a selected integration period over which the ADC values were accumulated, the integration period consisting of an integer number of cycles of the sample clock signal.
10. A digital timing loop circuit according to claim 8 and further comprising: means for selecting one of the even and odd ADC sample streams as closest in phase to a predetermined preamble pattern; error generating means for comparing the selected ADC sample stream values to predetermined expected peak values of the preamble pattern to form an error signal; means for coupling the error signal to the digital phase interpolating means for tracking.
11. A digital timing loop circuit for synchronizing a magnetic recording read channel comprising: an ADC for sampling an analog input signal responsive to a sampling clock signal; a phase detector for comparing a phase of the analog input signal as reflected in the ADC sample stream to the phase of the sampling clock signal to form a phase error signal; an integrator circuit for continually summing the phase error signal to form a phase select signal; a phase interpolator for digitally adjusting the phase of a reference clock signal that provides the sampling clock signal, responsive to the phase select signal, for aligning the sampling clock signal to the analog input signal during steady state operation; and a digital zero-phase restart circuit coupled to the integrator to adjust the phase select signal based upon an initial phase estimate at the beginning of a read operation, wherein the digital zero-phase restart circuit includes means for determining the initial phase estimate by an arctan lookup method based on even and odd ADC sample streams.
12. A zero-phase restart (ZPR) circuit for use in a magnetic read channel receiving first and second series of digital sample values to provide an initial phase estimate value, the ZPR circuit comprising: a first accumulator for accumulating the first digital sample values over a selected integration period to form an accumulated cosine value; a second accumulator for accumulating the second digital sample values over the same selected integration period to form an accumulated sine value; and an arctan lookup table coupled to the first and second accumulators to provide the initial phase estimate value as an arctan function of the accumulated sine and cosine values.
13. A zero-phase restart (ZPR) circuit according to claim 12 wherein the first and second accumulators each includes means for dividing the accumulated sine and cosine values, respectively, by a number corresponding to the selected integration period.
14. A zero-phase restart (ZPR) circuit according to claim 13 wherein the arctan lookup table comprises logic circuits.
15. A zero-phase restart (ZPR) circuit according to claim 13 wherein the arctan lookup table comprises a memory for storing phase estimate values.
16. A zero-phase restart (ZPR) circuit according to claim 13 wherein the arctan lookup table includes a read-only memory for storing phase estimate values.
17. A zero-phase restart (ZPR) circuit according to claim 13 wherein the arctan lookup table implements a half-size design by storing a selected one of either non-negative or non-positive input values.
18. A zero-phase restart (ZPR) circuit according to claim 12 and further comprising a control circuit for determining the selected integration period; the control circuit providing a control signal coupled to the first and second accumulators for clearing the accumulators at the end of the selected integration period.
19. A zero-phase restart (ZPR) circuit according to claim 18 wherein the control circuit is programmable so as to allow selection of the integration period under software control.
20. A zero-phase restart (ZPR) circuit according to claim 18 wherein the control circuit is programmable so as to allow selection of the integration period as a selected integer multiple number of cycles of the sampling clock signal.
21. A zero-phase restart (ZPR) circuit according to claim 18 and further comprising a register for storing the an initial phase estimate value provided by the arctan lookup table.
22. A zero-phase restart (ZPR) circuit for use in a magnetic read channel receiving first and second series of digital sample values ADC0, ADC1 to provide an initial phase estimate value, the ZPR circuit comprising: a first accumulator for accumulating the first digital sample values over a selected integration period to form an accumulated cosine value; a second accumulator for accumulating the second digital sample values over the same selected integration period to form an accumulated sine value; and a Peak_at_one logic circuit for comparing the accumulated sine value to the accumulated cosine value and providing a Peak_at_one logic signal indicating whether or not the first series of digital sample values (ADC0) correspond to zero crossing samples (sine), and the second series of digital sample values (ADC1) correspond to peak samples (cosine).
23. A zero-phase restart (ZPR) circuit according to claim 22 and further comprising an arctan lookup table coupled to the first and second accumulators to provide the initial phase estimate value as an arctan function of the accumulated sine and cosine values.
24. A digital timing loop circuit for use in a magnetic read channel comprising: an analog to digital converter means for sampling an analog input signal responsive to a sampling clock signal; a memory means for storing alternate samples from the analog to digital converter means so as to form even and odd streams of ADC samples representing orthogonal sine and cosine components of said analog input signal; means for forming an initial phase estimate value responsive to the even and odd ADC sample streams; and digital phase interpolating means for shifting the sampling clock signal responsive to the initial phase estimate value at the beginning of the read operation so as to bring the sampling clock signal into alignment with the said analog input signal without halting the sampling clock.
25. A digital timing loop circuit for use in a magnetic read channel comprising: an analog to digital converter means for sampling an analog input signal responsive to a sampling clock signal; a memory means for storing alternate samples from the analog to digital converter means so as to form even and odd streams of ADC samples; means for forming an initial phase estimate value responsive to the even and odd ADC sample streams; digital phase interpolating means for shifting the sampling clock signal responsive to the initial phase estimate value at the beginning of the read operation so as to bring the sampling clock signal into alignment with the said analog input signal without halting the sampling clock; and a multiplier for selectively multiplying alternate samples from the ADC by +1 or -1 to store in said memory means, so as to form said even and odd streams of the ADC samples representing orthogonal sine and cosine components of said analog input signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 6, 1999
October 23, 2001
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