A method of making a semiconductor chip assembly, including providing a dielectric element with a plurality of electrically conductive terminals, disposing an expander ring over the dielectric element so that a semiconductor chip on the dielectric layer is disposed in a central opening in the expander ring, and disposing an encapsulant in the gap between the expander ring and the semiconductor chip. The size of the gap is controlled to minimize the pressure exerted on the leads by the elastomer as it expands and contracts in response to changes in temperature. The semiconductor chip and expander ring may also be connected to a heat sink or thermal spreader with a compliant adhesive.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of making a plurality of semiconductor chip assemblies, said method comprising the steps of: I. providing a dielectric element having a top surface and a plurality of electrically conductive traces, wherein each electrically conductive trace has a terminal-end, a contact-end opposite the terminal-end, and an electrically conductive terminal disposed at the terminal-end; II. disposing a compliant layer on the top surface of the dielectric element; III. providing a plurality of semiconductor chips, each of the semiconductor chips having a face surface, a plurality of electrically conductive contacts disposed on the face surface, and a plurality of side surfaces which define the outer perimeter of the semiconductor chip; IV. adhering the face surface of each semiconductor chip to the compliant layer; V. providing a strip of expander rings, each of the expanders rings having a plurality of inner side walls which define a central opening; VI. disposing the strip of expander rings over the top surface of the dielectric element such that a) each of the semiconductor chips is associated with one of the expander rings; b) each of the semiconductor chips is disposed within the central opening of the associated expander ring; and c) a gap is formed between the outer perimeter of each the semiconductor chips and the inner side walls of the associated expander ring; VII. forming at least one lead connecting each semiconductor chip to the dielectric element by connecting at least one contact on the face surface of each semiconductor chip to the contact-end of one of the traces; and VIII. encapsulating each of the semiconductor chip assemblies by filling the gap and open spaces between the dielectric element, the compliant layer, the semiconductor chip and the expander ring with a liquid composition which is curable to an encapsulant; wherein w.gtoreq.{(CTE.sub.expander ring -CTE.sub.chip)X.sub.c }/{CTE.sub.encapsulant (1+2p)}; where w is the width of each gap; CTE.sub.chip is the coefficient of thermal expansion of one of the semiconductor chips; CTE.sub.expander ring is the coefficient of thermal expansion of the associated expander ring; X.sub.c is the shortest distance between a point on the outer perimeter of the semiconductor chip and the center of the semiconductor chip; CTE.sub.encapsulant is the coefficient of thermal expansion of the encapsulant; and p is the Poisson ratio of the encapsulant.
2. The method of claim 1, wherein the encapsulant is elastomeric, the dielectric element is a flexible, the terminals are disposed on the top surface of said flexible dielectric element, and the flexible dielectric element includes a plurality of plated vias, each of the plated vias being in electrical contact with one of the terminals.
3. The method of claim 2, further comprising the step of disposing a solder ball within each of the plated vias.
4. The method of claim 1, wherein the encapsulant is elastomeric; the dielectric element is flexible, has a bottom surface opposite the top surface, and a plurality of apertures; and the terminals are disposed on the bottom surface of the flexible dielectric element.
5. The method of claim 4, further comprising the steps of providing a coverlay; and sealing the apertures in the flexible dielectric element, prior to the encapsulating step, by laminating the coverlay to the bottom surface of the flexible dielectric element.
6. The method of claim 5, wherein the coverlay has a plurality of holes, each of which is aligned with one of the terminals on the flexible dielectric element and wherein said method further comprises the step of disposing a solder ball on each of the plurality of terminals.
7. The method of claim 1, wherein a) the semiconductor chip has a back surface opposite the face surface; and b) the method further comprises the steps of providing a strip of thermal spreaders, wherein each of the thermal spreaders has a beta surface; and adhering the beta surface of each thermal spreader to the back surface of one of the semiconductor chips with a first adhesive; and c) the encapsulating step further includes the step of filling open spaces between the thermal spreader; and the flexible dielectric element, the compliant layer, the semiconductor chip, and the expander ring, with the liquid composition.
8. The method of claim 7, wherein each of the thermal spreaders has an alpha surface opposite the beta surface and a plurality of relief slots.
9. The method of claim 8, further comprising the steps of providing a protective film; and sealing the relief slots in the strip of thermal spreaders, prior to the encapsulating step, by adhering the protective film to the alpha surface of the thermal spreaders.
10. The method of claim 1 wherein at least some of the plurality of leads are fan-out leads and at least some of the plurality of leads are fan-in leads.
11. The method of claim 1, further comprising the step of at least partially curing the liquid composition.
12. The method of claim 1, further comprising the step of electrically interconnecting the terminals to an external substrate.
13. A method of making a semiconductor chip assembly, said method comprising the steps of: I. providing a dielectric element having a top surface and a plurality of electrically conductive traces, wherein each electrically conductive trace has a terminal-end, a contact-end opposite the terminal-end, and an electrically conductive terminal disposed at the terminal-end; II. disposing a compliant layer on the top surface of the dielectric element; III. providing a semiconductor chip having a face surface, a plurality of electrically conductive contacts disposed on the face surface, and a plurality of side surfaces which define the outer perimeter of the semiconductor chip; IV. adhering the face surface of the semiconductor chip to the compliant layer; V. providing an expander ring having a plurality of inner side walls which define a central opening; VI. disposing the expander ring over the top surface of the dielectric element such that the semiconductor chips is disposed within the central opening of the expander ring and a gap is formed between the outer perimeter of the semiconductor chips and the inner side walls of the expander ring; VII. forming at least one lead connecting the semiconductor chip to the dielectric element by connecting at least one contact on the face surface of the semiconductor chip to the contact-end of one of the traces; and VIII. encapsulating the semiconductor chip assemblies by filling the gap and open spaces between the dielectric element, the compliant layer, the semiconductor chip and the expander ring with a liquid composition which is curable to an encapsulant; wherein w.gtoreq.{(CTE.sub.expander ring -CTE.sub.chip)X.sub.c }/{CTE.sub.encapsulant (1+2p)}; where w is the width of the gap; CTE.sub.chip is the coefficient of thermal expansion of the semiconductor chips; CTE.sub.expander ring is the coefficient of thermal expansion of the expander ring; X.sub.c is the shortest distance between a point on the outer perimeter of the semiconductor chip and the center of the semiconductor chip; CTE.sub.encapsulant is the coefficient of thermal expansion of the encapsulant; and p is the Poisson ratio of the encapsulant.
14. The method of claim 13 wherein the encapsulant is elastomeric and the dielectric element is flexible.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 5, 1999
October 30, 2001
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