A user-friendly, PCI bus-compliant plug-in management card is provided to evaluate a PCI bus in a host computer system for correct operation. The PCI management card is provided with a PCI bus controller ASIC for tracking error and fault conditions which may occur on a PCI bus and reporting such error and fault conditions locally or remotely over a computer network. The PCI bus controller ASIC may be implemented with a reset snoop which snoops the PCI bus for a bus reset; a clock snoop which snoops the PCI bus for a bus clock changing frequency or dying; a cycle timer which begins counting when a bus cycle starts, resets the counting when the bus cycle ends, and triggers an alarm indicating a hung cycle when the bus cycle has not ended after a predetermined time period; a cycle snoop which snoops the bus for any illegal handshake and any hung cycle triggered from the cycle timer; and an error capture which captures all error and failure conditions snooped from the reset snoop, the clock snoop, the cycle timer, and reports such error and failure conditions to a local processor for transmission to a host system, or to a remote system over a computer network for remote system management.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A bus monitoring apparatus for tracking operation of a bus in a host system, comprising: at least one of a local clock and a local reset which are separate and independent from the host system; and a bus monitor having operations controlled by at least one of said local clock and said local reset, for tracking events on the bus, wherein said events include error and fault conditions which may occur on the bus, including one or more of the following: (1) when a bus reset occurred unexpectedly; (2) when a bus clock stopped operating; (3) when a bus cycle started and never completed; and (4) when a bus cycle started and completed with an illegal handshake.
2. A bus monitoring apparatus as claimed in claim 1, wherein said bus monitor further reports occurrence of said events on the bus over a computer network for remote system management.
3. A bus monitoring apparatus as claimed in claim 2, wherein said bus includes one of a Peripheral Component Interface (PCI) bus, an Industry Standard Architecture (ISA) bus, an Extended Industry Standard Architecture (EISA) bus, and a Micro-Channel Architecture (MCA) bus, and wherein said events include error and fault conditions which may occur on the bus.
4. A bus monitoring apparatus as claimed in claim 1, wherein said bus includes a Peripheral Component Interface (PCI) bus.
5. A bus monitoring apparatus as claimed in claim 1, wherein said bus includes one of a Peripheral Component Interface (PCI) bus, an Industry Standard Architecture (ISA) bus, an Extended Industry Standard Architecture (EISA) bus, and a Micro-Channel Architecture (CA) bus for serving as an interconnect transportation mechanism to transport data between highly integrated peripheral devices, peripheral add-in boards and processor/memory subsystems of the host system.
6. A bus monitoring apparatus as claimed in claim 1, wherein said bus monitor comprises: a reset snoop which snoops the bus for a bus reset; a clock snoop which snoops the bus for a bus clock changing frequency; a cycle timer which begins when a bus cycle starts, resets when said bus cycle ends, and triggers an alarm indicating a hung cycle when the bus cycle has not ended after a predetermined time period; a cycle snoop which snoops the bus for any illegal handshake and any hung cycle triggered from the cycle timer; and an error capture which captures all error and failure conditions snooped from the reset snoop, the clock snoop, and the cycle snoop, and reports such error and failure conditions for system management.
7. A bus monitoring apparatus as claimed in claim 6, wherein said cycle timer comprises a programmable counter which begins counting in increments of time to determine whether the bus cycle has ended after said predetermined time period, wherein said reset snoop further snoops the bus to report whether the bus was reset, and wherein said clock snoop further snoops the bus to report whether the bus clock has died.
8. A bus monitoring apparatus as claimed in claim 7, wherein said clock snoop contains a clock snoop algorithm executed to snoop a faulty clock condition on the bus by: determining whether a synchronized clock indicating the local clock in synchronous with the bus clock exhibits a first logic state; when the synchronized clock exhibits said first logic state, resetting said counter and restarting said counting for said predetermined time; determining whether the synchronized clock has switched to a second logic state opposite to said first logic state during said counting; when the synchronized clock has not switched to said second logic state, determining whether said counting for said predetermined time period has expired; and when said counting for said predetermined time period has expired, determining that said faulty clock condition has occurred on the bus.
9. A bus monitoring apparatus as claimed in claim 7, wherein said cycle snoop contains a cycle snoop algorithm executed to snoop a faulty cycle condition on the bus by: determining whether a new cycle on the bus has started; when the new cycle on the bus has started, resetting said counter and restarting said counting for said predetermined time period; determining whether any of legal termination conditions is found on the bus; when any one of said legal termination conditions is found on the bus, awaiting for a new cycle; when none of said legal termination conditions is found on the bus, determining whether target frame and initiator ready signals are inactive; when the target frame and initiator ready signals are inactive, determines that an illegal handshake has occurred on the bus; when the target frame and initiator ready signals are not inactive, determining whether said counting for said predetermined time period has expired; and when said counting for said predetermined time period has expired, determines that said illegal handshake has occurred on the bus.
10. A bus monitoring apparatus as claimed in claim 6, wherein said reset snoop further snoops the bus to report to the local processor whether the bus was reset.
11. A bus monitoring apparatus as claimed in claim 6, wherein said clock snoop further snoops the bus to report to the local processor whether the bus clock has died.
12. A bus monitoring apparatus as claimed in claim 1, further comprising: a local reset and clock generator which provides said local reset and said local clock that are separate and independent from the host system; a power supply which provides optional power backup; a memory which stores configuration information and said operating system that is separate and independent from the host system; a processor which processes said configuration information and said operating system from said memory for operation; and a network controller which provides an interface to a computer network for communications with a remote system over said computer network.
13. A bus monitoring apparatus for tracking operation of a bus in a host system comprising: at least one of a local clock and a local reset which are separate and independent from the host system; a bus monitor having operations controlled by at least one of said local clock and said local reset, for tracking events on the bus; a local reset and clock generator which generates said local reset and said local clock that is separate and independent from a bus clock of the host system; a power supply source which provides said power supply; a memory which stores configuration information and an operating system that is separate and independent from the host system; a processor which processes said configuration information and said operating system from the memory for operation; and a network controller which provides an interface to a computer network for communications with a remote system over said computer network.
14. A bus monitoring apparatus as claimed in claim 5, wherein said host system is a host server on said computer network, and wherein said processor controls said network controller to transmit information indicating error and failure conditions occurred on the bus to a remote system for remote system management via said computer network.
15. A bus monitoring apparatus as claimed in claim 14, wherein said computer network comprises Ethernet, Token Ring, Fiber Data Distribution Interface (FDDI), Asynchronous Transfer Mode (ATM), and/or integrated 56-K modem.
16. A bus monitoring apparatus as claimed in claim 13, wherein said bus monitor comprises: a reset snoop which snoops the bus for a bus reset; a clock snoop which snoops the bus for a bus clock changing frequency; a cycle timer which begins when a bus cycle starts, resets when said bus cycle ends, and triggers an alarm indicating a hung cycle when the bus cycle has not ended after a predetermined time period; a cycle snoop which snoops the bus for any illegal handshake and any hung cycle triggered from the cycle timer; and an error capture which captures all error and failure conditions snooped from the reset snoop, the clock snoop, and the cycle snoop, and reports such error and failure conditions for system management.
17. A bus monitoring apparatus as claimed in claim 16, wherein said clock snoop contains a clock snoop algorithm executed to snoop a faulty clock condition on the bus by: determining whether a synchronized clock indicating the local clock in synchronous with the bus clock exhibits a first logic state; when the synchronized clock exhibits said first logic state, resetting said cycle timer for counting and restarting said counting for said predetermined time; determining whether the synchronized clock has switched to a second logic state opposite to said first logic state during said counting; when the synchronized clock has not switched to said second logic state, determining whether said counting for said predetermined time period has expired; and when said counting for said predetermined time period has expired, determining that said faulty clock condition has occurred on the bus.
18. A bus monitoring apparatus as claimed in claim 16, wherein said cycle snoop contains a cycle snoop algorithm executed to snoop a faulty cycle condition on the bus by: determining whether a new cycle on the bus has started; when the new cycle on the bus has started, resetting said cycle timer for counting and restarting said counting for said predetermined time period; determining whether any of legal termination conditions is found on the bus; when any one of said legal termination conditions is found on the bus, awaiting for a new cycle; when none of said legal termination conditions is found on the bus, determining whether target frame and initiator ready signals are inactive; when the target frame and initiator ready signals are inactive, determines that an illegal handshake has occurred on the bus; when the target frame and initiator ready signals are not inactive, determining whether said counting for said predetermined time period has expired; and when said counting for said predetermined time period has expired, determines that said illegal handshake has occurred on the bus.
19. A bus monitoring apparatus for tracking operation of a bus in a host system comprising: at least one of a local clock and a local reset which are separate and independent from the host system; and a bus monitor having operations controlled by at least one of said local clock and said local reset, for tracking events on the bus and reporting occurrence of said events including error and fault conditions, wherein said bus monitor comprises: a reset snoop which snoops the bus for a bus reset; a clock snoop which snoops the bus for a bus clock changing frequency; a cycle timer which begins when a bus cycle starts, resets when said bus cycle ends, and triggers an alarm indicating a hung cycle when the bus cycle has not ended after a predetermined time period; a cycle snoop which snoops the bus for any illegal handshake and any hung cycle triggered from the cycle timer; and an error capture which captures all error and failure conditions snooped from the reset snoop, the clock snoop, and the cycle snoop, and reports such error and failure conditions occurred on the bus for remote system management over a computer network.
20. A bus monitoring apparatus as claimed in claim 19, wherein said local clock and said bus clock are synchronized for said reset snoop, said clock snoop and said cycle snoop to snoop the bus for said error and failure conditions on the bus for remote system management over said computer network.
21. A bus monitoring apparatus as claimed in claim 19, wherein said cycle timer comprises a programmable counter which begins counting time to determine whether the bus cycle has ended after said predetermined time period.
22. A bus monitoring apparatus as claimed in claim 21, wherein said clock snoop contains a clock snoop algorithm executed to snoop a faulty clock condition on the bus by the steps of: determining whether a synchronized clock with the bus clock exhibits a first logic state; when the synchronized clock exhibits said first logic state, restarting said counting in increments of time for said predetermined time period; determining whether the synchronized clock has switched to a second logic state opposite to said first logic state during said counting; when the synchronized clock has not switched to said second logic state, determining whether said counting for said predetermined time period has expired; and when said counting for said predetermined time period has expired, determining that said faulty clock condition has occurred on the bus.
23. A bus monitor apparatus as claimed in claim 21, wherein said cycle snoop contains a cycle snoop algorithm executed to snoop a faulty cycle condition on the bus by the steps of: determining whether a new cycle on the bus has started; when the new cycle on the bus has started, restarting said counting for said predetermined time period; determining whether any of legal termination conditions pre-defined by standards specification is found on the bus; when any one of said legal termination conditions is found on the bus, awaiting for a new cycle; when none of said legal termination conditions is found on the bus, determining whether target frame (Frame#) and initiator ready (IRDY#) signals are inactive; when the target frame (Frame#) and initiator ready (IRDY#) signals are inactive, determines that an illegal handshake has occurred on the bus; when the target frame (Frame#) and initiator ready (IRDY#) signals are not inactive, determining whether said counting for said predetermined time period has expired; and when said counting for said predetermined time period has expired, determines that said illegal handshake has occurred on the bus.
24. A bus monitoring apparatus as claimed in claim 19, wherein said reset snoop further snoops the bus to report whether the bus was reset.
25. A bus monitoring apparatus as claimed in claim 19, wherein said clock snoop further snoops the bus to report whether the bus clock has died.
26. A card for tracking a bus in a host system for correct operation, comprising: a clock generator which generates a local clock that is separate and independent from a bus clock of the host system; a power supply which provides optional power backup; a memory which stores configuration information and an operating system that is separate and independent from the host system; a processor which processes said configuration information and said operating system from said memory for operation; a network controller which provides an interface to a computer network for communications with a remote system over said computer network; and a bus controller which is operatively connected to said clock generator, said power supply, said processor, and said network controller, and which tracks error and fault conditions on the bus and reports such error and fault conditions to said processor for remote system management over said computer network.
27. A card as claimed in claim 26, wherein said bus includes one of a Peripheral Component Interface (PCI) bus, an Industry Standard Architecture (ISA) bus, an Extended Industry Standard Architecture (EISA) bus, and a Micro-Channel Architecture (MCA) bus.
28. A card as claimed in claim 26, wherein said bus includes a Peripheral Component Interface (PCI) bus, and wherein said error and fault conditions on the bus include ones or all the followings: (1) when a PCI reset occurred unexpectedly; (2) when a PCI clock stopped operating; (3) when a PCI bus cycle started and never completed; and (4) when a PCI cycle started and completed with an illegal handshake.
29. A card as claimed in claim 28, wherein said bus controller comprises: a reset snoop unit which snoops the PCI bus for the PCI reset; a clock snoop unit which snoops the PCI bus for a PCI clock radically changing frequency or dying; a cycle timer which begins when a PCI bus cycle starts, resets when the PCI bus cycle ends, and triggers an alarm indicating a hung cycle when the PCI bus cycle has not ended after a predetermined time period; a cycle snoop unit which snoops the PCI bus for any illegal handshake and any hung cycle triggered from the cycle timer; and an error capture unit which captures the error and fault conditions snooped from the reset snoop unit, the clock snoop unit, the cycle snoop unit, and reports such error and fault conditions to the processor for remote system management over said computer network.
30. A card as claimed in claim 29, wherein said cycle timer comprises a programmable counter which begins counting in increments of time to determine whether the PCI bus cycle has ended after said predetermined time period.
31. A card as claimed in claim 30, wherein said clock snoop unit contains a PCI clock snoop algorithm executed to snoop a faulty PCI clock condition on said PCI bus by the steps of: determining whether a synchronized clock indicating the local clock in synchronous with the PCI bus clock exhibits a first logic state; when the synchronized clock exhibits said first logic state, resetting said counter and restarting said counting for said predetermined time; determining whether the synchronized clock has switched to a second logic state opposite to said first logic state during said counting; when the synchronized clock has not switched to said second logic state, determining whether said counting for said predetermined time period has expired; and when said counting for said predetermined time period has expired, determining that said PCI faulty clock condition has occurred on the PCI bus.
32. A card as claimed in claim 30, wherein said cycle snoop unit contains a PCI cycle snoop algorithm executed to snoop a faulty PCI cycle condition on said PCI bus by the steps of: determining whether a new PCI cycle on the PCI bus has started; when the new PCI cycle on the PCI bus has started, resetting said counter and restarting said counting for said predetermined time period; determining whether any of legal termination conditions defined by PCI Local Bus Specification, Revision 2.1 is found on the PCI bus; when any one of said legal termination conditions is found on the PCI bus, awaiting for a new PCI cycle; when none of said legal termination conditions is found on the PCI bus, determining whether target frame (Frame#) and initiator ready (IRDY#) signals are inactive; when the target frame (Frame#) and initiator ready (IRDY#) signals are inactive, determines that an illegal PCI handshake has occurred on the PCI bus; when the target frame (Frame#) and initiator ready (IRDY#) signals are not inactive, determining whether said counting for said predetermined time period has expired; and when said counting for said predetermined time period has expired, determines that said illegal PCI handshake has occurred on the PCI bus.
33. A card as claimed in claim 29, wherein said reset snoop unit further snoops the PCI bus to report to the local processor whether the PCI bus was reset.
34. A card as claimed in claim 29, wherein said clock snoop unit further snoops the PCI bus to report to the local processor whether the bus clock has died.
35. A card as claimed in claim 26, wherein said computer network comprises Ethernet, Token Ring, Fiber Data Distribution Interface (FDDI), Asynchronous Transfer Mode (ATM), and/or integrated 56-K modem.
36. A card for tracking operation of a bus in a host system, comprising: an operating system, a power supply, and a local clock which are separate and independent from the host system; and a bus controller operatively connected to said operating system, said power supply, and said local clock, for tracking error and fault conditions which may occur on the bus, and for reporting such error and fault conditions occurred on the bus for system management, said bus controller comprising: a reset snoop which snoops the bus for a bus reset; a clock snoop which snoops the bus for a bus clock changing frequency; a cycle timer which begins when a bus cycle starts, resets when said bus cycle ends, and triggers an alarm indicating a hung cycle when the bus cycle has not ended after a predetermined time period; a cycle snoop which snoops the bus for any illegal handshake and any hung cycle triggered from the cycle timer; and an error capture which captures all error and failure conditions snooped from the reset snoop, the clock snoop, and the cycle snoop, and reports such error and failure conditions for system management.
37. A card as claimed in claim 36, wherein said cycle timer comprises a programmable counter which begins counting in increments of time to determine whether the bus cycle has ended after said predetermined time period.
38. A card as claimed in claim 36, wherein said reset snoop further snoops the bus to report whether the bus was reset, and said clock snoop further snoops the bus to report whether the bus clock has died.
39. A card as claimed in claim 36, wherein said bus includes one a Peripheral Component Interface (PCI) bus, an Industry Standard Architecture (ISA) bus, an Extended Industry Standard Architecture (EISA) bus, and a Micro-Channel Architecture (MCA) bus for serving as an interconnect transportation mechanism to transport data between highly integrated peripheral devices, peripheral add-in boards and processor/memory subsystems of the host system.
40. A card as claimed in claim 36, wherein said error and fault conditions are reported via computer network, said computer network comprises Ethernet, Token Ring, Fiber Data Distribution Interface (FDDI), Asynchronous Transfer Mode (ATM), and/or integrated 56-K modem.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 29, 1998
October 30, 2001
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