A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize source identification information to selectively route data to different memory sources in a shared memory system. This permits, for example, data to be routed to only a portion of the memory sources associated with a given requester, thereby reducing the bandwidth to other memory sources and reducing overall latencies within the system. Among other possible information, the source identification information may include an identification of which memory source and/or which level of memory is providing the requested data, and/or an indication of what processor/requester and/or what type of instruction last modified the requested data.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of routing data in a multi-requester circuit arrangement including a plurality of requesters coupled to a plurality of memory sources, wherein each requester is associated with at least a portion of the plurality of memory sources, the method comprising: (a) responding to a memory request by a first requester among the plurality of requesters, including providing source identification information associated with the memory source that is returning the requested data; and (b) responsive to the source identification information, selectively routing the requested data to only a subset of the memory sources associated with the first requester.
2. The method of claim 1, wherein the plurality of requesters includes first and second processing units.
3. The method of claim 2, wherein the plurality of memory sources are organized into at least first and second levels, the first level including first and second memory sources respectively associated with the first and second processing units, and the second level including a third memory source shared by the first and second processing units.
4. The method of claim 3, wherein the first and second memory sources are primary cache memories, the plurality of sources further including first and second secondary cache memories respectively associated with the first and second processing units.
5. The method of claim 1, wherein the source identification information includes a memory level indicator that indicates a level of memory sourcing the requested data.
6. The method of claim 5, wherein at least one of the plurality of requesters is a processing unit, and wherein the source identification information further includes a processing unit indicator that identifies a processing unit if any from the plurality of requesters that modified the requested data.
7. The method of claim 5, wherein the source identification information further includes an instruction indicator that identifies an instruction if any that modified the requested data.
8. The method of claim 1, wherein the memory sources associated with the first requester includes a cache memory, the method further comprising allocating a directory entry in the cache memory without storing the requested data in the cache memory responsive to the source identification information.
9. The method of claim 1, wherein providing the source identification information associated with the memory source for the requested data includes: (a) generating in each of at least a portion of the memory sources a coherency response, at least one of the coherency responses including the source identification information; and (b) generating a combined response from the coherency responses, wherein selectively routing the requested data is responsive to the combined response.
10. The method of claim 9, further comprising transmitting the combined response at least to the memory source that is returning the requested data.
11. The method of claim 1, further comprising invalidating data stored in at least one memory source responsive to the source identification information.
12. The method of claim 1, further comprising selectively routing the requested data directly to the first requester responsive to the source identification information.
13. A method of routing data in a multi-processor circuit arrangement including first and second processors, each processor coupled to and associated with a plurality of memories, the method comprising: (a) responding to a memory request by the first processor by outputting requested data from one of the plurality of memories associated with the second processor, including indicating which of the plurality of memories associated with the second processor is sourcing the requested data; and (b) selectively routing the requested data to only a subset of the plurality of memories associated with the first processor based upon which of the plurality of memories associated with the second processor is sourcing the requested data.
14. The method of claim 13, wherein each of the first and second processors is associated with at least primary and secondary cache memories.
15. The method of claim 14, wherein each of the first and second processors is further associated with a tertiary cache memory.
16. The method of claim 14, further comprising allocating a directory entry in at least one of the primary and secondary cache memories associated with the first processor without storing the requested data therein based upon which of the plurality of memories associated with the second processor is sourcing the requested data.
17. The method of claim 14, further comprising invalidating data stored in at least one of the primary and secondary cache memories associated with the second processor based upon which of the plurality of memories associated with the second processor is sourcing the requested data.
18. A method of routing data in a multi-requester circuit arrangement including a plurality of requesters coupled to a plurality of memory sources, wherein each requester is associated with at least a portion of the plurality of memory sources, the method comprising: (a) responding to a memory request by a first requester among the plurality of requesters, including providing source identification information associated with the memory source that is returning the requested data; and (b) responsive to the source identification information, selectively routing the requested data directly to the first requester without routing the requested data to any of the memory sources associated with the first requester.
19. A circuit arrangement, comprising: (a) a plurality of memory sources; (b) a plurality of requesters coupled to the plurality of memory sources, each requester associated with at least a portion of the plurality of memory sources; and (c) a data routing circuit configured to selectively route data requested by the first requester to only a subset of the memory sources associated with the first requester responsive to source identification information provided by a memory source that is returning the requested data.
20. The circuit arrangement of claim 19, wherein the plurality of requesters includes first and second processing units, and wherein the plurality of memory sources are organized into at least first and second levels, the first level including first and second memory sources respectively associated with the first and second processing units, and the second level including a third memory source shared by the first and second processing units.
21. The circuit arrangement of claim 19, wherein the source identification information includes at least one of a memory level indicator that indicates a level of memory sourcing the requested data, a processing unit indicator that identifies a processing unit if any that modified the requested data, and an instruction indicator that identifies an instruction if any that modified the requested data.
22. The circuit arrangement of claim 19, wherein the memory sources associated with the first requester includes a cache memory, and wherein the data routing circuit is further configured to allocate a directory entry in the cache memory without storing the requested data in the cache memory responsive to the source identification information.
23. The circuit arrangement of claim 19, further comprising: (a) a snoop logic circuit configured to generate in each of at least a portion of the memory sources a coherency response, at least one of the coherency responses including the source identification information; and (b) a response combining logic circuit configured to generate a combined response from the coherency responses, wherein the data routing circuit is responsive to the combined response.
24. The circuit arrangement of claim 23, wherein the response combining logic circuit is configured to transmit the combined response at least to the memory source that is returning the requested data.
25. The circuit arrangement of claim 19, wherein the data routing circuit is further configured to invalidate data stored in at least one memory source responsive to the source identification information.
26. The circuit arrangement of claim 19, wherein the data routing circuit is further configured to selectively route the requested data directly to the first requester responsive to the source identification information.
27. A data processing system, comprising: (a) a plurality of memory sources; (b) a plurality of requesters coupled to the plurality of memory sources, each requester associated with at least a portion of the plurality of memory sources; and (c) a data routing circuit configured to selectively route data requested by the first requester to only a subset of the memory sources associated with the first requester responsive to source identification information provided by a memory source that is returning the requested data.
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January 11, 1999
November 6, 2001
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