In a logic circuit having PMOS pull-up devices and NMOS pull-down devices, the PMOS pull-up devices are sized relative to the NMOS pull-down devices according to the number of transistors that simultaneously turn on. In one embodiment, the PMOS transistor width is determined by multiplying the effective NMOS transistor width by a predetermined factor indicative of a current carrying ratio between one of the PMOS pull-up transistors and one of the NMOS pull-down transistors and dividing by the number of PMOS pull-up transistors that simultaneously turn on to charge the output node high. Where the PMOS pull-up devices are parallel-connected, the NMOS transistor width is divided by the number of NMOS transistors.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of sizing each of a plurality of PMOS pull-up transistors relative to the size of each of a plurality of NMOS pull-down transistors in a logic circuit, wherein respective pairs of the plurality of PMOS pull-up and NMOS pull-down transistors may receive corresponding ones of a plurality of input signals, the method comprising: selecting an NMOS transistor width; determining an effective NMOS transistor width from the NMOS transistor width; multiplying the effective NMOS transistor width by a predetermined factor indicative of a current carrying capacity ratio between one of the PMOS pull-up transistors and one of the NMOS pull-down transistors; dividing a result of the multiplying step by the number of parallel-connected transistors that simultaneously turn on to generate a PMOS transistor width; and sizing each of the PMOS pull-up transistors to the PMOS transistor width.
2. The method of claim 1, wherein each of the PMOS pull-up transistors is connected in parallel between a voltage supply and an output node, and each of the NMOS pull-down transistors is connected in series between the output node and ground potential.
3. The method of claim 2, wherein the effective NMOS transistor width is equal to the NMOS transistor width divided by the number of NMOS pull-down transistors.
4. The method of claim 1, wherein each of the PMOS pull-up transistors is connected in series between a voltage supply and an output node, and each of the NMOS pull-down transistors is connected in parallel between the output node and ground potential.
5. The method of claim 4, wherein the effective NMOS transistor width is equal to the NMOS transistor width multiplied by the number of NMOS pull-down transistors.
6. A method of minimizing silicon area of a selected circuit having a plurality of input signals received by a respective plurality of PMOS pull-up transistors and by a respective plurality of NMOS pull-down transistors, the method comprising: selecting an NMOS transistor width; determining an effective NMOS transistor width from the NMOS transistor width; multiplying the effective NMOS transistor width by a predetermined factor indicative of a current carrying capacity ratio between one of the PMOS pull-up transistors and one of the NMOS pull-down transistors; multiplying a result of the multiplying step by the number of input signals that simultaneously transition to the same logic state to generate a PMOS transistor width; and sizing each of the PMOS pull-up transistors to the PMOS transistor width.
7. The method of claim 6, wherein each of the PMOS pull-up transistors is connected in parallel between a voltage supply and an output node, and each of the NMOS pull-down transistors is connected in series between the output node and ground potential.
8. The method of claim 7, wherein the effective NMOS transistor width is equal to the NMOS transistor width divided by the number of NMOS pull-down transistors.
9. The method of claim 6, wherein each of the PMOS pull-up transistors is connected in series between a voltage supply and an output node, and each of the NMOS pull-down transistors is connected in parallel between the output node and ground potential.
10. The method of claim 9, wherein the effective NMOS transistor width is equal to the NMOS transistor width multiplied by the number of NMOS pull-down transistors.
11. A circuit comprising: a plurality of PMOS pull-up transistors connected between a voltage supply and an output node, each having a gate coupled to receive a corresponding one of a plurality of input signals, where each PMOS pull-up transistor is of a first width; a plurality of NMOS pull-down transistors connected between the output node and ground potential, each having a gate coupled to receive a corresponding one of the plurality of input signals, where each NMOS pull-down transistor is of a second width, wherein the first width is equal to the second width multiplied by a factor indicative of a current carrying ratio between one of the PMOS pull-up transistors and one of the NMOS pull-down transistors and divided by the number of input signals that simultaneously transition to the same logic state.
12. The circuit of claim 11, wherein the PMOS pull-up transistors are connected in parallel between the output node and the supply voltage, and the NMOS pull-down transistors are connected in series between the output node and ground potential.
13. The circuit of claim 11, wherein the PMOS pull-up transistors are connected in series between the output node and the supply voltage, and the NMOS pull-down transistors are connected in parallel between the output node and ground potential.
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March 8, 2000
November 13, 2001
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