Semiconductor processing methods of forming integrated circuitry, and in particular, methods of forming such circuitry utilizing dual damascene technology, and resultant integrated circuitry constructions are described. In one embodiment, a substrate is provided having a circuit device. At least three layers are formed over the substrate and through which electrical connection is to be made with the circuit device. The three layers comprise first and second layers having an etch stop layer interposed therebetween. A contact opening is formed through the three layers and a patterned masking layer is formed over the three layers to define a conductive line pattern. Material of an uppermost of the first and second layers is selectively removed relative to the etch stop layer and defines a trough joined with the contact opening. Conductive material is subsequently formed within the trough and contact opening. In another embodiment, a contact opening is formed through a plurality of layers and has an aspect ratio of no less than about 10:1. A trench is defined in an uppermost layer of the plurality of layers proximate the contact opening. Conductive material is formed within the contact opening and at least a portion of the trench, with the conductive material being in electrical communication.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor processing method of forming integrated circuitry comprising: providing a conductive line formed over a substrate, the conductive line having a conductive portion and an insulative cap received on the conductive portion; forming at least three layers over the substrate and cap, the three layers comprising first and second layers having an etch stop layer interposed therebetween; in a common masking step, forming a contact opening through the at least three layers to the insulative cap over the conductive line; after forming the contact opening to the insulative cap, etching the insulative cap to expose the conductive portion of the conductive line; forming a layer of photoresist over the substrate and into the contact opening onto the conductive portion of the line; patterning the photoresist to define a conductive line pattern, at least some of the photoresist being received within the contact opening on the conductive portion of the conductive line after the patterning; and while photoresist is within the contact opening on the conductive line portion, selectively removing material of an uppermost of the first and second layers relative to the etch stop layer and defining a trough joined with the contact opening.
2. The semiconductor processing method of claim 1 wherein at least some of the insulative cap remains over the conductive portion of the line after the etching.
3. The semiconductor processing method of claim 1 wherein the etching of the insulative cap exposes less than an entirety of the width of the conductive portion.
4. The semiconductor processing method of claim 1 wherein the conductive portion exposed by the etching has the same width as the contact opening.
5. The semiconductor processing method of claim 1 wherein the photoresist received on the conductive portion of the line has a thickness which is less than that of the insulative cap.
6. The semiconductor processing method of claim 1 further comprising removing the photoresist from over the conductive portion of the line and thereafter filling the contact opening with conductive material, the filling comprising: depositing a layer comprising titanium within the opening; depositing a layer comprising titanium nitride within the opening over the layer comprising titanium; rapid thermal processing the titanium nitride comprising and titanium comprising layers within the opening, the rapid thermal processing comprising a first temperature ramping step and a discrete second temperature ramping step; and after the rapid thermal processing, depositing aluminum to within the opening.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 6, 1998
November 20, 2001
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