Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The network further includes a network of dummy polysilicon lines that are configured to overlie selected dummy active regions. The network of dummy polysilicon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.
Legal claims defining the scope of protection, as filed with the USPTO.
1. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise, the computer readable media comprising: program instructions for designing a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions, the plurality of dummy active regions being separated from the plurality of active regions by at least a bloat distance; and program instructions for designing a network of dummy polysilicon lines being configured to overlie selected dummy active regions, the network of dummy polysilicon lines that overlie the selected dummy active regions functioning as dummy gates that interconnect the plurality of dummy active regions; wherein the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions define capacitor structure locations for the network of on-chip capacitive structures.
2. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 1, further comprising: program instructions for designing a power supply mask; and program instructions for performing a logical AND operation between the power supply mask and the network of dummy polysilicon lines, the logical AND operation defining a power overlap area that identifies a location for a power supply contact.
3. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 1, further comprising: program instructions for designing a ground rail mask; program instructions for performing a logical AND operation between an inverted network of dummy polysilicon lines and the plurality of dummy active regions to produce a modified dummy active pattern; and program instructions for performing a logical AND operation between the ground rail mask and the modified dummy active pattern to produce a ground overlap area that identifies a location for a ground rail contact.
4. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 1, wherein the program instructions for designing the plurality of dummy active regions further comprises: program instructions for providing a mask having the plurality of active regions; program instructions for bloating the plurality of active regions to produce a plurality of bloated active regions mask; program instructions for inverting the plurality of bloated active regions mask to produce an inverted plurality of bloated active regions mask; and program instructions for performing a logical AND operation between the inverted plurality of bloated active regions mask and a mask having the plurality of dummy active regions to produce a modified dummy active regions mask.
5. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 4, further comprising: program instructions for performing a logical OR operation between the modified dummy active regions mask and the mask having the plurality of active regions to produce a final active region and dummy active region mask.
6. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 4, wherein the program instructions for designing the network of dummy polysilicon lines further comprises: program instructions for providing a mask having a grid of dummy polysilicon lines; program instructions for bloating a plurality of active polysilicon lines to produce a plurality of bloated polysilicon lines mask; program instructions for inverting the plurality of bloated polysilicon lines mask to produce an inverted plurality of bloated polysilicon lines mask; program instructions for performing a logical AND operation between the inverted plurality of bloated polysilicon lines mask and the mask having the grid of dummy polysilicon lines to produce an intermediate grid of dummy polysilicon lines mask; and program instructions for performing a logical AND operation between the inverted plurality of bloated active regions mask and the intermediate grid of dummy polysilicon lines mask to produce a modified grid of dummy polysilicon lines mask.
7. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 6, further comprising: program instructions for performing a logical OR operation between the modified grid of dummy polysilicon lines mask and the plurality of active polysilicon lines to produce a final polysilicon line and dummy polysilicon line mask.
8. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 7, wherein the final polysilicon line and dummy polysilicon line mask and the final active region and dummy active region mask are used to form the network of on-chip capacitive structures for suppressing power supply inductive noise.
9. Computer readable media having program instructions for designing a network of on-chip capacitive structures, the computer readable media comprising: program instructions for designing a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions, the plurality of dummy active regions being separated from the plurality of active regions; and program instructions for designing a network of dummy polysilicon lines being configured to overlie selected dummy active regions, and the dummy polysilicon lines that overlie the selected dummy active regions define capacitor structure locations for the network of on-chip capacitive structures.
10. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 9, further comprising: program instructions for designing a power supply mask; and program instructions for performing a logical AND operation between the power supply mask and the network of dummy polysilicon lines, the logical AND operation defining a power overlap area that identifies a location for a power supply contact.
11. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 9, further comprising: program instructions for designing a ground rail mask; program instructions for performing a logical AND operation between an inverted network of dummy polysilicon lines and the plurality of dummy active regions to produce a modified dummy active pattern; and program instructions for performing a logical AND operation between the ground rail mask and the modified dummy active pattern to produce a ground overlap area that identifies a location for a ground rail contact.
12. Computer readable media having program instructions for carrying out a method for designing a network of on-chip capacitive structures used in suppressing power supply inductive noise as recited in claim 9, wherein the program instructions for designing the plurality of dummy active regions further comprises: program instructions for providing a mask having the plurality of active regions; program instructions for bloating the plurality of active regions to produce a plurality of bloated active regions mask; program instructions for inverting the plurality of bloated active regions mask to produce an inverted plurality of bloated active regions mask; and program instructions for performing a logical AND operation between the inverted plurality of bloated active regions mask and a mask having the plurality of dummy active regions to produce a modified dummy active regions mask.
13. Computer readable media having program instructions for designing on-chip capacitive structures, the computer readable media comprising: program instructions for designing a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions, the plurality of dummy active regions being separated from the plurality of active regions; the program instructions for designing a plurality of dummy active regions further includes program instructions for, providing a mask having the plurality of active regions; bloating the plurality of active regions to produce a plurality of bloated active regions mask; inverting the plurality of bloated active regions mask to produce an inverted plurality of bloated active regions mask; and performing a logical AND operation between the inverted plurality of bloated active regions mask and a mask having the plurality of dummy active regions to produce a modified dummy active regions mask; wherein program instructions for designing a network of dummy polysilicon lines being configured to overlie selected dummy active regions, and the dummy polysilicon lines that overlie the selected dummy active regions define capacitor structure locations for the on-chip capacitive structures.
14. Computer readable media having program instructions for designing on-chip capacitive structures as recited in claim 13, further comprising: program instructions for designing a power supply mask; and program instructions for performing a logical AND operation between the power supply mask and the network of dummy polysilicon lines, the logical AND operation defining a power overlap area that identifies a location for a power supply contact.
15. Computer readable media having program instructions for designing on-chip capacitive structures as recited in claim 13, further comprising: program instructions for designing a ground rail mask; program instructions for performing a logical AND operation between an inverted network of dummy polysilicon lines and the plurality of dummy active regions to produce a modified dummy active pattern; and program instructions for performing a logical AND operation between the ground rail mask and the modified dummy active pattern to produce a ground overlap area that identifies a location for a ground rail contact.
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November 30, 1999
December 4, 2001
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