A method is disclosed for forming the lower storage node and contact for capacitors on a semiconductor wafer. The method includes an etch back process to remove a portion of the silicon oxide layer around the mouth of the contact hole to produce a rounded shoulder where the walls of the contact hole meet the face of the silicon oxide layer. When a contact plug is formed during a subsequent deposition process, the rounded shoulder results in local enlargement of the contact plug as well as filleting of reentrant corners. The contact plug therefore sustains substantially reduced mechanical stress during subsequent wafer cleaning processes. This stress reduction results in a reduced rate of lower node collapse and increased production yield of finished product.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a lower storage node of a capacitor for dynamic random access memory (DRAM), the storage node positioned on a semiconductor wafer, the semiconductor wafer comprising a substrate, a silicon oxide layer covering the substrate, the method comprising: forming a first transitory layer with a predetermined thickness on the silicon oxide layer; forming a recess in a predetermined region of the first transitory layer; forming a second transitory layer on the semiconductor wafer covering the first transitory layer and the recess; performing a first dry etching process to remove the second transitory layer from the top of the first transitory layer and from the bottom of the recess, leaving only an peripheral spacer on the wall of the recess; performing a second dry etching process to vertically remove the silicon oxide layer within the spacer down to the surface of the substrate to form a contact hole; performing an etch back process to remove a portion of the silicon oxide layer around the mouth of the contact hole to produce a rounded shoulder where the walls of the contact hole meet the face of the silicon oxide layer; forming a first conductive layer on the semiconductor wafer, the first conductive layer covering the silicon oxide layer and filling the contact hole; forming a second conductive layer with a predetermined thickness on the first conductive layer; performing a photolithographic process to form a first photoresist layer that defines a position and a size of the lower storage node of the capacitor; and performing a third dry etching process to vertically remove the first and the second conductive layers, where not masked by the first photoresist layer, down to the face of the silicon oxide layer to complete the lower storage node.
2. The method of claim 1 wherein a raised landing pad is positioned on the substrate below the recess, to serve as an electrical connector between the lower storage node of the capacitor and the substrate.
3. The method of claim 2 wherein the landing pad is made of polysilicon.
4. The method of claim 1 wherein the silicon oxide layer further comprises two embedded straight and parallel bit lines made of polysilicon.
5. The method of claim 1 wherein the formation of the recess comprises: performing a photolithographic process to form a second photoresist layer that defines a position and a width of the recess in the first transitory layer; and performing a dry etching process to vertically remove the first transitory layer, where it is not masked by the second photoresist layer, down to the silicon oxide layer.
6. The method of claim 1 wherein the first transitory layer and the second transitory layer are both made of polysilicon.
7. The method of claim 1 wherein the first conductive layer and the second conductive layer are made of a conductive material that contains silicon, such as polysilicon or amorphous silicon.
8. The method of claim 1 wherein the etching gas of the etch back process is Cl.sub.2 /HBr/SF.sub.6 with a process temperature of 50.degree. C. and a process power of 1300W.
9. A method of forming a lower storage node of a capacitor for dynamic random access memory (DRAM), the storage node positioned on a semiconductor wafer, the semiconductor wafer comprising a substrate, a silicon oxide layer covering the substrate, the method comprising: forming a first polysilicon layer with a predetermined thickness on the silicon oxide layer; forming a recess in a predetermined region of the first polysilicon layer; forming a second polysilicon layer on the semiconductor wafer that covers both the first polysilicon layer and the recess; performing a first dry etching process to remove the second polysilicon layer from the top of the first polysilicon layer and from the bottom of the recess to form an annular spacer on the wall of the recess; performing a second dry etching process to vertically remove the silicon oxide layer within the spacer down to the surface of the substrate to form a contact hole; performing an etch back process using Cl.sub.2 /HBr/SF.sub.6 etch gas to remove a portion of the silicon oxide layer around the mouth of the contact hole to produce a rounded shoulder where the walls of the contact hole meet the face of the silicon oxide layer; forming a first conductive layer on the semiconductor wafer, the first conductive layer covering the silicon oxide layer and filling the contact hole; forming a second conductive layer with a predetermined thickness on the first conductive layer; performing a photolithgraphic process to form a first photoresist layer that defines a position and a size of the lower storage node of the capacitor; and performing a third dry etching process to vertically remove the first and the second conductive layers, where not masked by the first photoresist layer, down to the substrate to complete the lower storage node of the capacitor.
10. The method of claim 9 wherein a raised landing pad is positioned on the substrate below the recess, to serve as an electrical connector between the lower storage node of the capacitor and the substrate.
11. The method of claim 10 wherein the landing pad is made of polysilicon.
12. The method of claim 9 wherein the silicon oxide layer further comprises two parallel linear bit lines made of polysilicon.
13. The method of claim 9 wherein the formation of the recess comprises: performing a photolithographic process to form a second photoresist layer that defines a position and a width of the recess in the first transitory layer; and performing a dry etching process to vertically remove the first transitory layer, where it is not masked by the second photoresist layer, down to the substrate.
14. The method of claim 9 wherein the first conductive layer and the second conductive layer are made of a conductive material that contains silicon, such as polysilicon or amorphous silicon.
15. The method of claim 9 wherein Cl.sub.2 /HBr/SF.sub.6 is employed as etching gas in the etch back process, the process temperature is 50.degree. C. and the process power is 1300 W.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 28, 2000
December 11, 2001
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