Multiple memory access streams issued by multiple memory controller access devices are used for accessing DRAM or other memory. The memory controller can arbitrate among requests for multiple requestors, such as in a multiprocessor environment. Coherency can be provided by snooping a write buffer and returning, write buffer contents directly, in response to a read request for a matching address. Coherency need not be implemented through the entirety of an address space and preferably can be enabled for only selected portion or portions of the address space, reducing unnecessary coherency checking overhead.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory controller system for processing received memory requests, said received memory requests being requests within a predefined address space, comprising: at least first and second memory controllers for outputting first and second memory request streams, each stream including an address and read/write control signals; a predecoder which receives said memory requests and which outputs said memory requests, along with information regarding said memory requests, to an arbiter; wherein said arbiter receives said memory requests and outputs control signals which control said first and second memory controllers such that said control signals, output by said arbiter, determine the order in which said memory requests are granted, using said information output by said predecoder, wherein the timing of said first memory request stream is independent of the timing of said second memory request stream.
2. A memory controller as claimed in claim 1 wherein said received memory requests include requests received from at least first and second different requesters.
3. A memory controller as claimed in claim 2 wherein said first and second different requesters are first and second processors of a multiprocessor system.
4. A memory controller system as claimed in claim 1 wherein said first and second memory controllers and said arbiter are part of a system-on-a-chip which contains, on a single integrated circuit, at least a processor and said first memory controller.
5. A memory controller as claimed in claim 1 further comprising a slow system I/O port state machine for outputting at least a third memory request stream.
6. A memory controller as claimed in claim 1 wherein a plurality of said received memory requests are received in a first order and wherein said arbiter controls said first and second memory controllers to provide memory requests, to a memory, in an order different from said first order.
7. A memory controller as claimed in claim 1 further comprising coherency control circuitry which provides data coherency for requests in a first portion of said address space and disables data coherency procedures for requests in a second portion of said address space.
8. A memory controller as claimed in claim 7 wherein said coherency control circuitry is configurable to select said first portion of said address space.
9. A memory controller as claimed in claim 1 further comprising coherency control configurable between at least a first state which provides coherency for all requests in said address space and a second state in which data coherency procedures are disabled in at least a portion of said address space.
10. A memory controller as claimed in claim 1 further comprising a write buffer for holding data from write requests prior to writing said data, and coherency control circuitry which causes output of data from said write buffer in response to a read request for an address matching a write address for data stored in said write buffer.
11. A system as claimed in claim 1, wherein said arbiter outputs said control signals so as to determine the order in which to grant requests in response to whether a requester is a slow device.
12. A system as claimed in claim 1, wherein said arbiter outputs said control signals so as to determine the order in which to grant requests in response to the amount of data requested.
13. A system as claimed in claim 1, wherein said arbiter outputs said control signals so as to determine the order in which to grant requests in response to occupancy of a write buffer.
14. A memory controller system for processing memory requests received from at least first and second requestors, said received memory requests being requests within a predefined address space wherein said received memory requests are received in a first order, comprising: at least first and second memory controllers for controlling first and second memory request streams, each stream including an address and read/write control signals; a predecoder which receives said memory requests and which outputs said memory requests, along with information regarding said memory requests, to an arbiter; wherein said arbiter receives said memory requests from said at least first and second requestors and outputs control signals which control said at least first and second memory controllers such that said control signals output by said arbiter determine the order in which said memory requests are granted, using said information output by said predecoder to control said at least first and second memory request streams, providing memory requests, to a memory, in an order different from said first order.
15. A memory controller system as claimed in claim 14 wherein said first and second requestors are first and second processors of a multiprocessor system.
16. A memory controller system as claimed in claim 14 wherein said first and second memory controllers and said arbiter are part of a system-on-a-chip which contains, on a single integrated circuit, at least a processor and said first memory controller.
17. A memory controller as claimed in claim 14 for further comprising coherency control circuitry which provides data coherency for requests in a first portion of said address space and disables data coherency procedures for requests in a second portion of said address space.
18. A memory controller as claimed in claim 14 further comprising a write buffer for holding data from write requests prior to writing said data, and coherency control circuitry which causes output of data from said write buffer in response to a read request for an address matching a write address for data stored in said write buffer.
19. A memory control method for processing received memory requests, said received memory requests being requests within a predefined address space, comprising: providing at least first and second state machines for outputting first and second memory request streams, each stream including an address and read/write control signals; providing a predecoder which receives said memory requests and which outputs said memory requests, along with information regarding said memory requests, to an arbiter; said arbiter outputting control signals for controlling said first and second state machines such that said control signals output by said arbiter determine the order in which said memory requests are granted, using said information output by said predecoder to output memory requests in said first memory request stream at times independent of the timing of requests in said second memory request stream.
20. A method as claimed in claim 19 wherein a plurality of said received memory requests are received in a first order and wherein requests in said first and second memory streams are provided to a memory in an order different from said first order.
21. A method as claimed in claim 19 further comprising performing coherency checking procedures for requests in a first portion of said address space in the absence of performing said coherency checking procedures for requests in a second portion of said address space.
22. A method as claimed in claim 21 further comprising receiving at least a first signal for selecting said first portion of said address space.
23. A method as claimed in claim 19 further comprising receiving at least a first signal for selecting between at least a first state which provides coherency for all requests in said address space and a second state in which data coherency procedures are disabled in at least a portion of said address space.
24. A method, as claimed in claim 19, further comprising: storing data from write requests in a write buffer, prior to writing said data, and outputting data from said write buffer in response to a read request for an address matching a write address for data stored in said write buffer.
25. A method, as claimed in claim 19, further comprising: storing write data from a first write request for a first address, in a write buffer; and overwriting said write data, in said write buffer, with write data from a subsequent write request for said first address, if said subsequent write request is received before said write data is written from said write buffer to memory.
26. Apparatus for processing received memory requests, said received memory requests being requests within a predefined address space, comprising: first means for outputting a first memory request stream including an address and read/write control signal; second means for outputting a second memory request stream including an address and read/write control signal; predecoder means for receiving memory requests and outputting said memory requests along with information regarding said memory requests to a means for controlling said first and second means for outputting; said means for controlling said first and second means for outputting, receiving said memory requests and outputting control signals which control said first and second means for outputting such that said means for controlling determines the order in which said memory requests are granted, using said information output by said predecoder means to output memory requests in said first memory request stream at times independent of the timing of requests in said second memory request stream.
27. Apparatus as claimed in claim 26 wherein a plurality of said received memory requests are received in a first order and wherein said means for controlling controls said first and second means for outputting such that requests in said first and second memory streams are provided to a memory in an order different from said first order.
28. Apparatus as claimed in claim 26 further comprising means for performing coherency checking procedures for requests in a first portion of said address space in the absence of performing said coherency checking procedures for requests in a second portion of said address space.
29. Apparatus, as claimed in claim 26, further comprising: means for storing data from write requests, prior to writing said data, and means for outputting data from said means for storing, in response to a read request for an address matching a write address for data stored in said means for storing.
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December 21, 1998
December 11, 2001
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