Semiconductor memory device

1. A semiconductor memory device comprising: a plurality of banks, and wherein column decoders of all banks are activated, at a time of executing a refresh counter test, based on a write command or read command supplied after a refresh command has been supplied.

2. The semiconductor memory device according to claim 1, wherein said plurality of banks are mounted in a transverse direction, in a longitudinal direction or in both longitudinal and transverse directions.

3. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is of a synchronous type in which a command, at least, is entered in synchronization with a clock.

4. A semiconductor memory device comprising: a plurality of word lines, a plurality of bit lines, a plurality of memory cells each being mounted in a matrix form at a point of intersection between each of said word lines and bit lines; a plurality of input/output lines each being mounted corresponding to each of said bit lines used to input and output data fed from outside to said corresponding memory cell, memory cell arrays each having a plurality of column switches to connect said corresponding bit lines to said corresponding input/output lines; row decoders to activate any one of said plurality of word lines; a plurality of banks each having a column decoder to activate any one of said plurality of column switches; a refresh counter to renew its counter value in accordance with a refresh command; first controlling means for outputting a first controlling signal to activate any one of said row decoders of said plurality of banks based on renewed counter values every time said refresh command is supplied; and second controlling means for outputting a second controlling signal to activate column decoders of all banks based on a write command or read command supplied after said refresh command has been supplied.

5. The semiconductor memory device according to claim 4, further comprising a third controlling means for outputting a third controlling signal used to activate any one of said column decoders of said plurality of banks based on an output obtained by ANDing said first controlling signal with said second controlling signal.

6. The semiconductor memory device according to claim 4, wherein said memory cell array has a plurality of voltage clamping means for clamping a voltage of each of said input/output lines at a predetermined level and wherein said semiconductor memory device further comprises a fourth controlling means for outputting a fourth controlling signal used to activate each of said plurality of voltage clamping means of banks to which said first controlling signal is not supplied.

7. The semiconductor memory device according to claim 4, wherein said plurality of banks are mounted in a transverse direction, in a longitudinal direction or in both longitudinal and transverse directions.

8. The semiconductor memory device according to claim 4, wherein said semiconductor memory device is of a synchronous type in which a command, at least, is entered in synchronization with a clock.