A semiconductor device comprises a semiconductor substrate having an area in which a circuit element is formed, and a passivation film formed on an upper surface of the semiconductor substrate,at least part of the passivation film being uneven shaped film, an upper surface of which is formed into an uneven shape independent of a shape of a lower surface of the passivation film layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a semiconductor substrate having a circuit element; a base layer formed on the semiconductor substrate, the base layer including an insulating layer; and a passivation film formed on the base layer such that a lower surface thereof is planar, and such that at least part of an upper surface thereof is formed into an uneven shape in which a film thickness of thin portions is one fifth to one third of a film thickness of thick portions.
2. The semiconductor device as set forth in claim 1 , wherein the uneven shape is formed at least above an area in which the circuit element is formed.
3. The semiconductor device as set forth in claim 2 , wherein at least one of the thin portions and the thick portions are arranged so as to be a closest packing structure.
4. The semiconductor device as set forth in claim 3 , wherein the thin or thick portions are regularly arranged such that the each center of adjacent thin or thick portions form a regular triangle.
5. The semiconductor device as set forth in claim 2 , wherein the thin portion is formed so as to be the minimum thickness capable of protecting the circuit element.
6. The semiconductor device as set forth in claim 2 , wherein at least one of corner portions of the each thin portion and each thick portion defined by the each thin portion is rounded.
7. The semiconductor device as set forth in claim 2 , wherein the passivation film includes a first insulating layer and a second insulating layer laminated on the first insulating layer and having etching selectivity with respect to the first insulating layer, and portions where the second insulating layer is selectively removed and thereby only the first insulating layer remains constitute the thin portions.
8. The semiconductor device as set forth in claim 2 , wherein the passivation film includes first silicon oxide film, silicon nitride film laminated on the first silicon oxide film and second silicon oxide film laminated on the silicon nitride film, the thin portions are constituted by the first silicon oxide film and the silicon nitride film, and the thick portions are constituted by the first silicon oxide film, the silicon nitride film and the second silicon oxide film.
9. The semiconductor device as set forth in claim 1 , wherein the passivation film is formed on the planarized insulating layer as the base layer.
10. The semiconductor device as set forth in claim 9 , wherein the base layer is planarized by the CMP method.
11. The semiconductor device as set forth in claim 9 , wherein the base layer includes the insulating layer planarized by the CMP method and a wiring section formed on a part of the insulating layer.
12. The semiconductor device as set forth in claim 1 , wherein the uneven shaped film is formed into a shape such that a plurality of independent thick portions are provided on the passivation film which is substantially planar.
13. The semiconductor device as set forth in claim 1 , wherein the uneven shaped film is formed in a vicinity area of a circuit element generates a large amount of heat, the vicinity area includes at least a part of above the circuit element.
14. The semiconductor device as set forth in claim 1 , wherein the base layer on which the passivation film is to be formed, includes insulating film covers the circuit element, and conductive sections formed on a part of the insulating film, and the uneven shaped film is arranged between the conductive sections.
15. The semiconductor device as set forth in claim 14 , wherein an electric potential difference exists between the conductive sections.
16. The semiconductor device as set forth in claim 15 , wherein the conductive sections includes conductive sections exposed from the passivation film, and the uneven shaped film is arranged between the exposed conductive sections having the electric potential difference therebetween.
17. The semiconductor device as set forth in claim 16 , wherein the passivation film includes at least one of silicon-rich SiN film, silicon-rich SiO film and silicon-rich SiON film.
18. The semiconductor device as set forth in claim 1 , wherein a base layer on which the passivation film is to be formed including insulating film, and at least two wiring sections formed on a part of the insulating film, and the uneven shaped film has at least one groove portion of the thin portion extending in parallel with at least one of the wiring sections.
19. The semiconductor device as set forth in claim 1 further comprising: at least two electrode pads exposed from the passivation film, and wherein the passivation film has an uneven surface between the electrode pads.
20. The semiconductor device as set forth in claim 1 , wherein the passivation film is formed directly on the insulating layer, the uneven shape of the upper surface of the passivation film not corresponding to a shape of an upper surface of the insulating layer.
21. A semiconductor device comprising: a semiconductor substrate having a circuit element; a base layer formed on the semiconductor substrate, the base layer including an insulating layer; and a passivation film formed into an uneven shape on the base layer and including a plurality of insulating layers, each insulating layer being materially different from any abutting insulating layer, wherein thin portions of the passivation film are formed by removing the uppermost insulating layer of the passivation film and thick portions of the passivation film are constituted by all the insulating layers of the passivation film.
22. A semiconductor device comprising: a semiconductor substrate having a circuit element that generates heat; and a passivation film formed into an uneven shape over an upper surface of the semiconductor substrate and including a plurality of insulating layers, each insulating layer being materially different from any abutting insulating layer, wherein thin portions of the passivation film are formed by removing the uppermost insulating layer of the passivation film and thick portions of the passivation film are constituted by all the insulating layers of the passivation film.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 20, 1999
January 1, 2002
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