A semiconductor package and a corresponding method of forming this package are provided. The semiconductor package includes a paddle and a semiconductor device mounted on the paddle. A passive electronic component is also mounted on the paddle and spaced apart from the semiconductor device. Interconnects provide a conductive path from a bonding pad of the semiconductor device to a bonding pad of the passive electronic component such that the passive electronic component and semiconductor device are operatively connected.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package, comprising: a leadframe comprising a plurality of finger-like members bounding a paddle area, wherein said finger-like members have conductive contacts; a conductive paddle located in said paddle area; a semiconductor device mounted on said paddle; and a passive electronic component spaced apart from said semiconductor device and mounted on said conductive paddle, wherein said passive electronic component includes a ceramic having a first side and a second side, said first side being bonded to said conductive paddle and said second side having a first conductive layer formed thereon.
2. The semiconductor package of claim 1 , wherein said passive electronic component includes a first isolation layer deposited on said first conductive layer.
3. The semiconductor package of claim 2 , wherein said passive electronic component includes a second conductive layer deposited on said first isolation layer.
4. The semiconductor package of claim 3 , wherein said passive electronic component includes a second isolation layer deposited on said second conductive layer.
5. A semiconductor package, comprising: a leadframe comprising a plurality of finger-like members bounding a paddle area, wherein said finger-like members have conductive contacts; a conductive paddle located in said paddle area; a semiconductor device mounted on said paddle; and a capacitor spaced apart from said semiconductor device and mounted on said conductive paddle.
6. The semiconductor package of claim 1 , further comprising an interconnect providing a conductive path from a bonding pad of said semiconductor device to a bonding pad of said passive electronic component.
7. The semiconductor package of claim 1 , further comprising an electrically isolated region within said paddle.
8. The semiconductor package of claim 1 , further comprising an interconnect providing a conductive path from said electrically isolated region to a bonding pad of said passive electronic component.
9. The semiconductor package of claim 1 , wherein said passive electronic component includes: a first conductive layer having a first side and a second side, said first side of said first conductive layer being bonded to said paddle; a first isolation layer bonded to said second side of said first conductor; and a second conductive layer bonded to said first isolation layer.
10. The semiconductor package of claim 1 , wherein said passive electronic component is an inductor.
11. The semiconductor package of claim 1 , wherein said passive electronic component is a transformer.
12. A semiconductor package, comprising: a leadframe comprising a plurality of finger-like members bounding a paddle area, wherein said finger-like members have conductive contacts and said paddle area is deep-down set; a conductive paddle located in said paddle area; a semiconductor device mounted on said paddle; and a passive electronic component spaced apart from said semiconductor device and mounted on said conductive paddle.
13. The semi-conductor package of claim 12 , further comprising an interconnect providing a conductive path from a bonding pad of said semiconductor device to a bonding pad of said passive electronic component.
14. The semiconductor package of claim 12 , further comprising an electrically isolated region within said paddle.
15. The semiconductor package of claim 14 , further comprising an interconnect providing a conductive path from said electrically isolated region to a bonding pad of said passive electronic component.
16. The semiconductor package of claim 12 wherein said paddle area has a front side and a back side, said front side being mated to the semiconductor device and said backside being at least partially exposed.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 22, 1998
January 1, 2002
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