Delay optimized mapping for programmable gate arrays with multiple sized lookup tables

1. A process for mapping logic nodes to a plurality of sizes of lookup tables in a programmable gate array, comprising: selectively collapsing into a first single node, a node and its predecessor nodes as a function of delay factors associated with the plurality of sizes of lookup tables and a maximum of delay factors associated with the predecessor nodes; selecting one of the sizes of lookup tables to implement the first single node if an associated cut-size of the first single node is less than or equal to the number of inputs to the one size; selectively collapsing into a second single node a node and its predecessor nodes as a function of the delay factors and the maximum delay factor increased by a selected value if a lookup table size was not selected for the first single node; and selecting one of the sizes of lookup tables to implement the second single node if an associated cut-size of the second single node is less than or equal to the number of inputs to the one size.

2. The process of claim 1 , further comprising selecting a predetermined size of lookup table as a default size to implement the node if a size was not selected for either the first or second single nodes.

3. The process of claim 1 , further comprising: if a size was selected for the first single node, assigning a delay factor to the first single node; if a size was selected for the second single node, assigning a delay factor to the second single node; repeating the steps of selectively collapsing and selecting sizes for all the nodes in a network.

4. The process of claim 3 , wherein the delay factor assigned to the first single node is the maximum of delay factors associated with the predecessor nodes, and the delay factor assigned to the second single node is the maximum of delay factors associated with the predecessor nodes plus the selected value.

5. The process of claim 3 , further comprising mapping the nodes in an order such that all predecessors of a node are mapped before the node is mapped.

6. The process of claim 5 , further comprising replacing the nodes with lookup tables having the sizes from the selecting steps.

7. The process of claim 6 , wherein replacing begins with output nodes and proceeds in an order such that all nodes receiving an input from a node are processed before the node.

8. The process of claim 6 , further comprising combining groups of selected ones of the lookup tables into respective single lookup tables using the plurality of sizes of lookup tables.

9. The process of claim 8 , further comprising: determining a maximum path delay value of delay values associated with respective input/output paths through the programmable gate array; and combining a group of selected ones of the lookup tables into a single lookup table only if the path delay value associated with the single lookup table does not exceed the maximum path delay value.

10. A process for mapping a logic node and its predecessor logic nodes to one of a plurality of sizes of lookup tables in a programmable gate array, each of the plurality of sizes of lookup tables having an associated delay factor, comprising: (a) initializing a counter to a selected value; (b) selecting one of the sizes of lookup tables; (c) collapsing into a single node the logic node and the ones of the predecessor logic nodes having delay factors greater than a maximum of delay factors associated with the predecessor logic nodes plus the counter value minus the delay factor of the one size lookup table; (d) if the single node has an associated cut-size that is less than or equal to the number of inputs to the one size lookup table, mapping to the one size lookup table the logic nodes that have been collapsed into the single node and that are within a cut of the single node; (e) if the associated cut-size of the single node is greater than the number of inputs of the one size lookup table, selecting another one of the sizes of lookup tables to use as the one size; (f) repeating steps (c) through (e) until the logic nodes within a cut are mapped or cut-sizes for all the sizes of lookup tables have been considered in mapping; (g) if the logic nodes within a cut have not been mapped to one of the sizes of lookup tables and cut-sizes for all the sizes of lookup tables have been considered in mapping, incrementing the counter value; and (h) repeating steps (b) through (g) until the counter value equals a least of delay factors of the sizes of lookup tables.

11. The process of claim 10 , wherein the sizes are selected in order from the lookup table having the least delay factor to the lookup table having the greatest delay factor.

12. A process for mapping a logic node and its predecessor logic nodes to one of a plurality of sizes of lookup tables in a programmable gate array, each of the plurality of sizes of lookup tables having an associated delay factor, comprising: (a) initializing a collapse factor as a function of a maximum of respective delay factors associated with the predecessor logic nodes, wherein the collapse factor is greater than the maximum of the delay factors of the predecessor logic nodes; (b) selecting one of the sizes of lookup tables; (c) collapsing into a single node the logic node and the ones of the predecessor logic nodes having delay factors greater than the collapse factor minus the delay factor of the one size lookup table; (d) if the single node has an associated cut-size that is less than or equal to the number of inputs to the one size lookup table, mapping to the one size lookup table the logic nodes collapsed into the single node that are within a cut of the single node; (e) if the associated cut-size of the single node is greater than the number of inputs of the one size lookup table, selecting another one of the sizes of lookup tables to use as the one size; (f) repeating steps (c) through (e) until the logic nodes within a cut are mapped or all the sizes of lookup tables have been considered in mapping.

13. The process of claim 12 , further comprising: (g) if the logic nodes within a cut have not been mapped to one of the sizes of lookup tables and cut-sizes for all the sizes of lookup tables have been considered in mapping, increasing the collapse factor; and (h) repeating steps (b) through (g) until the logic nodes within a cut are mapped or the collapse factor exceeds a predetermined value.

14. The process of claim 13 , wherein the sizes are selected in order from the lookup table having a least delay factor to the lookup table having the greatest delay factor.

15. The process of claim 13 , wherein the predetermined value is a least of the delay factors of the sizes of lookup tables.

16. A process for mapping logic nodes comprising: (a) arranging the nodes to be processed in topological order such that all fan-ins for a node are processed before the node is processed; (b) getting the next node to be processed; (c) selecting the smallest size LUT; (d) collapsing into a single node the node in process and all predecessor nodes having a delay greater than the maximum delay of the predecessor nodes minus the LUT delay of the selected LUT; (e) if the network formed by collapsing these nodes has a cut size no greater than that of the selected LUT, mapping the collapsed node into the selected LUT and assigning the LUT delay to the collapsed node; (f) if the cut sizes don't match and there are more LUT sizes available, selecting a larger LUT size; (g) repeating steps d, e, and f until all LUT sizes have been tried or the node is mapped; (h) if mapping did not occur for any LUT size when all those predecessor nodes having delay greater than the maximum delay of the predecessor nodes minus the LUT delay of the selected LUT were collapsed into a single node, then increasing delay by a factor i and repeat steps c through g until the factor i is equal to delay of the fastest LUT; (i) selecting a fastest LUT and assigning the node to the fastest LUT; and (j) repeating the process for all nodes.

17. The process of claim 16 , wherein a smaller lookup table is faster than a larger lookup table.

18. The process of claim 16 , wherein the factor i is a least of the delay factors of the sizes of LUTs.

19. A process for using slack information to determine LUT output delay, wherein the LUT output delay is the time interval between when a signal arrives at a primary input to the time when the signal arrives at the output of the LUT, comprising: (a) arranging LUTs to be processed in topological order such that all fan-outs from an original LUT are processed before the original LUT is processed; and (b) for each original LUT: (b1) determining the maximum set of predecessor original LUTs that can be covered by a new LUT such that the LUT output delay of the new LUT is less than or equal to the LUT output delay of the original LUT plus the slack value of the original LUT; (b2) replacing the original LUT and the maximum set of predecessor original LUTs with the new LUT; and (b3) assigning slack values to fan-ins of the new LUT.