A multiple cycle memory access unit issues a memory access load or store, delaying a predetermined number of instruction cycles between it activation and its initial data transfer. The multiple cycle memory access unit controls a predetermined plural number of accesses and operates independently and in parallel with the instruction flow of the data processor. The multiple cycle memory access unit delays a predetermined number of instruction cycles between sequential data transfers of the predetermined number of data transfers. This predetermined period may be the same as the initial delay or it may be determined independent of the initial delay. The operation of the multiple cycle memory access unit is subject to predication on an instruction specified data registers. The multiple cycle memory access unit preferably provides predetermined register number cycling among the plural data registers. The multiple cycle memory access unit preferably aborts operation, stops and saves its internal state on a predetermined event.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data processor operating in instruction cycles including: a data memory having a plurality of address locations, a plurality of data registers, an instruction dispatch/decode unit responsive to a stream of instructions to decode instructions and activate corresponding functional units, said stream of instructions including at least one normal memory access instruction and at least one multiple cycle memory access instruction; a normal memory access unit connected to said data memory, said plurality of data register and said instruction dispatch/decode unit for data transfer between a predetermined address location of said data memory and a predetermined one of said data registers, said normal memory access unit initiating data transfer during an instruction cycle of actuation by said instruction dispatch/decode unit in response to a normal memory access instruction; a multiple cycle memory access unit connected to said data memory, said plurality of data registers and said instruction dispatch/decode unit for data transfer between a predetermined address location of the data memory and a predetermined one of the data registers, the multiple cycle memory access unit delaying a predetermined number of instruction cycles between activation by said instruction dispatch/decode unit in response to a multiple cycle memory access instruction and initial data transfer; wherein the multiple cycle memory access unit performs the data transfers independently and in parallel with the data processor's instruction flow, once the multiple cycle memory access unit has been activated.
2. The data processor of claim 1 , wherein the multiple cycle memory access unit data transfer is a load, from the data memory to the data registers.
3. The data processor of claim 1 , wherein the multiple cycle memory access unit data transfer is a store, from the data registers to the data memory.
4. The data processor of claim 1 , wherein the operations of the multiple cycle memory access unit are subject to predication on an instruction specified one of said data registers, whereby the operation subject to predication aborts upon a predetermined state in the instruction specified data register.
5. The data processor of claim 4 , wherein the multiple cycle memory access unit operations subject to predication are data accesses.
6. The data processor of claim 4 , wherein the multiple cycle memory access unit operations subject to predication are data writes.
7. The data processor of claim 4 , wherein the multiple cycle memory access unit operations subject to predication are both data accesses and data writes.
8. The data processor of claim 4 , wherein the multiple cycle memory access unit aborts the operation on predication failure and continues with the next operation.
9. The data processor of claim 4 , wherein the multiple cycle memory access unit aborts the operation on predication failure and stops operation.
10. The data processor of claim 1 , wherein the multiple cycle memory access unit aborts operation and stops on a predetermined event.
11. The data processor of claim 10 , wherein the predetermined event is an external interrupt.
12. The data processor of claim 10 , wherein the predetermined event is an internal interrupt.
13. The data processor of claim 10 , wherein the predetermined event is a forward branch taken.
14. The data processor of claim 10 , wherein the predetermined event is a subroutine call.
15. The data processor of claim 1 , wherein the multiple cycle memory access unit's internal state is saved into instruction visible and alterable memory when the unit aborts operation and stops.
16. The data processor of claim 15 , where the instruction visible memory is control registers.
17. The data processor of claim 1 , wherein the multiple cycle memory access unit can be enabled and disabled.
18. The data processor of claim 17 , wherein the multiple cycle memory access unit is enabled and disabled via instructions.
19. The data processor of claim 15 , wherein the multiple cycle memory access unit is enabled and disabled via bits in a control register.
20. The data processor of claim 1 , wherein the multiple cycle memory access unit is loaded and activated by special instructions.
21. The data processor of claim 1 , wherein the multiple cycle memory access unit is loaded and activated by normal instructions in a special mode.
22. A data processor operating in instruction cycles including: a data memory having a plurality of address locations, a plurality of data registers, an instruction dispatch/decode unit responsive to a stream of instructions to decode instructions and activate corresponding functional units, said stream of instructions including at least one multiple cycle memory access instruction; a multiple cycle memory access unit connected to said data memory, said plurality of data registers and said instruction dispatch/decode unit for data transfer between a predetermined address location of the data memory and a predetermined one of the data registers, the multiple cycle memory access unit delaying a predetermined number of instruction cycles between activation by said instruction dispatch/decode unit in response to a multiple cycle memory access instruction and initial data transfer; wherein the multiple cycle memory access unit executes a predetermined number of data transfers in response to a single activation by said instruction dispatch/decode unit.
23. The data processor of claim 22 , wherein the multiple cycle memory access unit delays a predetermined number of instruction cycles between sequential data transfers of the predetermined number of data transfers.
24. The data processor of claim 23 , wherein the predetermined period is the same as the initial delay.
25. The data processor of claim 23 , wherein the predetermined period is independent of the initial delay.
26. The data processor of claim 22 , wherein the multiple cycle memory access unit provides predetermined register number cycling among said plurality of data registers.
27. The data processor of claim 26 , wherein the register number cycling is between an instruction specified data register and a data register having a next greater register number.
28. The data processor of claim 26 , wherein the register number cycling is between two register pairs, a first register pair consisting of an instruction specified data register and a data register having a next greater register number and a second register pair consisting of a data register having a register number two greater than the instruction specified data register and a data register having a register number three greater than the instruction specified data register.
29. The data processor of claim 26 , wherein the register number cycling begins with an instruction specified data register and employs a data register having a next greater register number each following register access until a data register having a largest register number is reached.
30. The data processor of claim 26 , wherein the register number cycling begins with an instruction specified data register and employs a data register having a next smaller register number each following register access until a data register having a smallest register number is reached.
31. The data processor of claim 26 , wherein the register number cycling begins with an instruction specified data register, employs a data register having a next larger register number each following register access until a data register having a largest register number is reached, and employs a data register having a smallest register number following access to the data register having the largest register number.
32. The data processor of claim 26 , wherein the register number cycling begins with an instruction specified data register, employs a data register having a next smaller register number each following register access until a data register having a smallest register number is reached, and employs a data register having a largest register number following access to the data register having the smallest register number.
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May 19, 1999
January 8, 2002
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