A display control circuit of the present invention includes: a clock generator for generating a first clock signal having a single frequency; a frequency divider for dividing the frequency of the first clock signal generated by the clock generator, thereby providing a second clock signal; a selection signal generation section for generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected; a selector for selecting one of the first clock signal and the second clock signal based on the selection signal; and a display circuit for performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A display control circuit, comprising: a clock generator for generating a first clock signal having a single frequency; a frequency divider for dividing the frequency of the first clock signal generated by the clock generator, thereby providing a second clock signal; a selection signal generation section for generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected; a selector for selecting one of the first clock signal and the second clock signal based on the selection signal; and a display circuit for performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
2. A display control circuit according to claim 1 , wherein the frequency divider further comprises a blocking section for blocking the frequency divider from receiving the first clock signal when the selector selects the first clock signal.
3. A display control circuit according to claim 1 , further comprising a voltage adjustment section for adjusting a display device driving voltage based on the selection signal when the display circuit variably controls a timing of a control signal output to a display device.
4. A display control circuit, comprising: a clock generator for generating a first clock signal having a single frequency; a frequency multiplier for multiplying the frequency of the first clock signal generated by the clock generator, thereby providing a second clock signal; a selection signal generation section for generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected; a selector for selecting one of the first clock signal and the second clock signal based on the selection signal; and a display circuit for performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
5. A display control circuit according to claim 4 , further comprising a voltage adjustment section for adjusting a display device driving voltage based on the selection signal when the display circuit variably controls a timing of a control signal output to a display device.
6. A display control method, comprising the steps of: generating a selection signal upon which one of a binary display mode and a gray-scale display mode is selected; selecting one of a first clock signal and a second clock signal obtained by dividing the frequency of the first clock signal based on the selection signal; and performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
7. A display control method according to claim 6 , further comprising the step of generating one of a display setting voltage for the binary display mode and a display setting voltage for the gray-scale display mode based on the selection signal.
8. A display control method, comprising the steps of: generating a selection signal upon which one of a binary display and a gray-scale display is selected; selecting one of a first clock signal and a second clock signal obtained by multiplying the frequency of the first clock signal based on the selection signal; and performing one of the binary display mode and the gray-scale display mode using the selected clock signal.
9. A display control method according to claim 8 , further comprising the step of generating one of a display setting voltage for the binary display mode and a display setting voltage for the gray-scale display mode based on the selection signal.
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October 28, 1998
January 15, 2002
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