A CPU (1) outputs a data signal (DI) in synchronization with an internal clock signal (Iclk). A device (101), which is an integrated circuit, is connected with a delay circuit (10) which is placed outside the device (101). The delay circuit (10) delays the internal clock signal (Iclk) for a delay time shorter than one cycle thereof, and thereby supplies the delayed signal as a delay clock signal (Dclk) to the device (101). A data transfer control circuit (2) delays the data signal (DI) for the delay time of the delay clock signal (Dclk) according to the delay clock signal (Dclk) and a control signal (CS) outputted by the CPU (1), and outputs the delayed data signal as a data signal (DE) to an external device. Since the external device operates in accordance with a control signal (WR) outputted synchronously with the internal clock signal (Iclk), a hold time corresponding to the delay time can be ensured. Thus, an external device, which requires a long hold time, is connectable with the device (101).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a CPU operating in synchronization with an internal clock signal; a terminal, being exposed outside said semiconductor device so as to be connectable with a delay circuit which delays said internal clock signal for a predetermined delay time and thereby outputs a delayed signal as a delay clock signal, for receiving said delay clock; and a data transfer control circuit for relaying a data signal transferred between said CPU and an external device with a delay for said delay time according to said delay clock signal supplied through said terminal.
2. The semiconductor device of claim 1 , wherein said semiconductor device, referring to said terminal as a first terminal, further comprises a second terminal, being exposed outside said semiconductor device so as to be connectable with said delay circuit, for supplying said internal clock signal to said delay circuit.
3. The semiconductor device of claim 1 , further comprising a third terminal, being exposed outside said semiconductor device, for receiving a clock signal from an outside of said semiconductor device, wherein said clock signal received by said third terminal is transferred to said CPU as said internal clock signal.
4. The semiconductor device of claim 3 , further comprising an internal clock signal generation circuit, being interposed between said third terminal and said CPU, for generating said internal clock signal according to said clock signal.
5. The semiconductor device of claim 1 , wherein said data transfer control circuit comprises: a data hold circuit for holding said data signal, which is inputted to said data transfer control circuit, in synchronization with said delay clock signal; a buffer control circuit for outputting a first control signal, being active during a period delayed for said delay time behind a period during which said data signal is inputted, according to a second control signal, which said CPU outputs in synchronization with said internal clock to inform said buffer control circuit that a transfer of said data signal is started and ended, and to said delay clock signal; and a tri-state buffer for outputting said data signal held by said data hold circuit to an outside of said data transfer control circuit only when said first control signal is active.
6. The semiconductor device of claim 5 , wherein said buffer control circuit comprises: an S/R flip-flop, having a set input and a reset input, for outputting said first control signal; a first logical AND circuit for transferring said delay clock signal to said set input only when said second control signal has a predetermined first value; and a second logical AND circuit for transferring said delay clock signal to said reset input only when said second control signal has a predetermined second value.
7. The semiconductor device of claim 5 , wherein said data transfer control circuit further comprises a selection circuit, interposed between said buffer control circuit and said tri-state buffer, for selectively transferring either said first control signal or a third control signal which said CPU outputs to inform said external device that said data signal is transferred, to said tri-state buffer according to a selection signal.
8. The semiconductor device of claim 7 , wherein said CPU has a register, and a signal held by said register is inputted to said selection circuit as a selection signal.
9. The semiconductor device of claim 1 , further comprising a tri-state buffer for relaying another data signal transferred between said CPU and another external device, wherein said tri-state buffer passes said another data signal therethrough only when a control signal, which said CPU outputs to inform said another external device that said another data signal is transferred, is active.
10. The semiconductor device of claim 1 , wherein said data signal relayed by said data transfer control circuit is transferred from said CPU to said external device.
11. The semiconductor device of claim 1 , further comprising said delay circuit, wherein said delay circuit is connected with said terminal, and said delay time is set shorter than one cycle of said internal clock.
12. The semiconductor device of claim 11 , wherein said delay circuit comprises: a first inverter for receiving said internal clock; a second inverter for outputting said delay clock; and a low-pass filter interposed between said first and second inverters having a capacitor and a resistor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 10, 1999
February 5, 2002
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