In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising a semiconductor substrate, a gate insulating film formed thereon and a gate electrode formed on the gate insulating film, wherein the gate electrode includes a polycrystalline silicon layer which is a laminate of a plurality of polycrystalline silicon films, each polycrystalline silicon film having crystal grains of substantially columnar structure, wherein each of the polycrystalline silicon films has a thickness, and wherein, for each of the plurality of polycrystalline silicon films, each crystal grain of a respective polycrystalline silicon film, of the plurality of polycrystalline silicon films, has a size substantially spanning the thickness of said respective polycrystalline silicon film.
2. The semiconductor device according to claim 1 , wherein the gate insulating film is a gate oxide film, formed by thermal oxidation of the semiconductor substrate.
3. The semiconductor device according to claim 2 , wherein the plurality of polycrystalline silicon films have an impurity incorporated therein for electrically activating polycrystalline silicon of the plurality of polycrystalline silicon films.
4. The semiconductor device according to claim 1 , wherein the gate insulating film is a silicon oxide film.
5. The semiconductor device according to claim 4 , wherein the plurality of polycrystalline silicon films have an impurity incorporated therein for electrically activating polycrystalline silicon of the plurality of polycrystalline silicon films.
6. The semiconductor device according to claim 1 , wherein adjacent films of said plurality of polycrystalline silicon films have a border therebetween.
7. The semiconductor device according to claim 1 , wherein the semiconductor substrate is a silicon substrate.
8. The semiconductor device according to claim 7 , wherein the gate insulating film is a silicon oxide film.
9. The semiconductor device according to claim 8 , wherein the plurality of polycrystalline silicon films have an impurity incorporated therein for electrically activating polycrystalline silicon of the plurality of polycrystalline silicon films.
10. The semiconductor device according to claim 1 , which includes an MOS transistor, the gate electrode being a gate electrode of said MOS transistor.
11. The semiconductor device according to claim 10 , further comprising source and drain regions of the MOS transistor, provided at sides of the gate electrode, in the semiconductor substrate.
12. The semiconductor device according to claim 1 , wherein said size substantially spanning the thickness of the respective polycrystalline silicon film is a height of the crystal grains.
13. The semiconductor device according to claim 1 , wherein adjacent films of said plurality of polycrystalline silicon films directly contact each other.
14. A semiconductor device comprising a semiconductor substrate, a gate insulating film formed thereon and a gate electrode formed on the gate insulating film, the gate electrode including a polycrystalline layer which is a laminate of a plurality of films of electrically conducting polycrystalline material, the plurality of films being in electrical contact with each other, each of the plurality of films having crystal grains of substantially columnar structure, wherein each of the plurality of films has a thickness, and wherein, for each of the plurality of films, each crystal grain of a respective film, of the plurality of films, has a size substantially spanning the thickness of said respective film.
15. The semiconductor device according to claim 14 , wherein adjacent films of the plurality of films have a border therebetween.
16. The semiconductor device according to claim 14 , wherein said size substantially spanning the thickness of said respective film is a height of the crystal grains.
17. The semiconductor device according to claim 14 , wherein adjacent films of the plurality of films directly contact each other.
18. A semiconductor device comprising a semiconductor substrate, a gate insulating film on the semiconductor substrate and a gate electrode on the gate insulating film, wherein the gate electrode includes a polycrystalline layer which includes a stack of a plurality of films of polycrystalline material, all of the plurality of films being connected electrically, wherein each of the plurality of films has a thickness, and wherein, for each of the plurality of films of polycrystalline material, each crystal grain of a respective film of polycrystalline material, of the plurality of films of polycrystalline material, has a size substantially spanning the thickness of said respective film.
19. The semiconductor device according to claim 18 , wherein the semiconductor substrate is a silicon substrate, and the polycrystalline material is polycrystalline silicon.
20. The semiconductor device according to claim 18 , wherein said stack of a plurality of films of polycrystalline material includes films of a conducting material of a material different than the polycrystalline material, interposed between adjacent films of said plurality of films of polycrystalline material.
21. The semiconductor device according to claim 18 , wherein the plurality of films of polycrystalline material have an impurity incorporated therein for electrically activating the polycrystalline material.
22. The semiconductor device according to claim 21 , which includes an MOS transistor, the gate electrode being a gate electrode of said MOS transistor.
23. The semiconductor device according to claim 18 , wherein the crystal grains are of substantially columnar structure, and wherein said size of the crystal grains substantially spanning the thickness of said respective film is a height of the crystal grains.
24. The semiconductor device according to claim 14 , wherein adjacent films of the plurality of films directly contact each other.
25. A semiconductor device comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate and a gate electrode formed on the gate insulating film, wherein the gate electrode includes a polycrystalline silicon layer which is a stack of a plurality of polycrystalline silicon films, each of the polycrystalline silicon films comprising crystal grains of substantially columnar structure, and the polycrystalline silicon films having an interface between adjacent polycrystalline silicon films of said plurality of polycrystalline silicon films.
26. The semiconductor device according to claim 25 , wherein adjacent films of said plurality of polycrystalline silicon films directly contact each other.
27. The semiconductor device according to claim 25 , wherein the plurality of polycrystalline silicon films have an impurity incorporated therein for electrically activating polycrystalline silicon of the plurality of polycrystalline silicon films.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 8, 2000
February 12, 2002
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