In a characteristics evaluation circuit incorporated into a semiconductor wafer, a dummy element is connected to at least two pads, and a depletion type MOS transistor is connected between the pads. A fuse is connected to a gate of the depletion type MOS transistor, and a gate voltage control pad is connected to the fuse.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A characteristics evaluation circuit incorporated into a semiconductor wafer, comprising: a dummy element connected to at least two pads; a depletion type MOS transistor connected between said pads; a fuse connected to a gate of said depletion type MOS transistor; and a gate voltage control pad connected to said fuse.
2. The characteristics evaluation circuit as set forth in claim 1 , wherein said dummy element comprises a MOS transistor.
3. The characteristics evaluation circuit as set forth in claim 1 , wherein said dummy element comprises a resistor.
4. The characteristics evaluation circuit as set forth in claim 1 , wherein said dummy element comprises a capacitor.
5. The characteristics evaluation circuit as set forth in claim 1 , being incorporated into each semiconductor chip of said semiconductor wafer.
6. The characteristics evaluation circuit as set forth in claim 1 , being incorporated into a scribe area of said semiconductor wafer.
7. The characteristics evaluation circuit as set forth in claim 1 , being incorporated into a characteristics evaluation area having the same size of semiconductor chip of said semiconductor wafer.
8. A method for evaluating a semiconductor characteristics evaluation circuit comprising a dummy element connected to at least two pads, a depletion type MOS transistor connected between said pads, a fuse connected to a gate of said depletion type MOS transistor, and a gate voltage control pad connected to said fuse, said method comprising the steps of: applying an appropriate voltage to said gate voltage control pad so as to turn OFF said depletion type MOS transistor; placing probes on said pads to measure characteristics of said dummy element after said appropriate voltage is applied to said gate voltage control pad; and cutting said fuse after the characteristics of said dummy element are measured.
9. The method as set forth in claim 8 , wherein said dummy element comprises a MOS transistor.
10. The method as set forth in claim 8 , wherein said dummy element comprises a resistor.
11. The method as set forth in claim 8 , wherein said dummy element comprises a capacitor.
12. The method as set forth in claim 8 , wherein said characteristics evaluation circuit is incorporated into each semiconductor chip of said semiconductor wafer.
13. The method as set forth in claim 8 , wherein said characteristics evaluation circuit is incorporated into a scribe area of said semiconductor wafer.
14. The method as set forth in claim 8 , wherein said characteristics evaluation circuit is incorporated into a characteristics evaluation area having the same size of semiconductor chips of said semiconductor wafer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 1, 2000
February 12, 2002
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