A method for forming dielectric protection in different regions of a semiconductor device, in accordance with the present invention, includes forming structures in a first region and a second region. A dielectric layer is grown on surfaces of the structures and in between the structures in the first region and the second region. The dielectric layer is damaged in the second region to provide an altered layer which is etchable at a faster rate than the dielectric layer in the first region. The dielectric layer in the first region and the altered layer in the second region are etched to provide a dielectric protection layer having a first thickness in the first region and a second thickness in the second region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming dielectric protection in different regions of a semiconductor device comprising the steps of: forming structures in a first region and a second region; growing a dielectric layer on surfaces of the structures and in between the structures in the first region and the second region; damaging the dielectric layer in the second region without removing the dielectric layer to provide an altered layer which is etchable at a faster rate than the dielectric layer in the first region; and wet etching the dielectric layer in the first region and the altered layer in the second region to provide a dielectric protection layer having a first thickness in the first region and a second thickness in the second region.
2. The method as recited in claim 1 , wherein the first region is an array region and the second region is a support region.
3. The method as recited in claim 1 , wherein the first thickness is greater than the second thickness.
4. The method as recited in claim 1 , wherein the step of growing a dielectric layer on surfaces includes the step of growing an oxide layer on sidewalls of the structures and in between the structures.
5. The method as recited in claim 1 , wherein the step of damaging the dielectric layer in the second region to provide an altered layer includes the step of exposing the dielectric layer in the second region to a plasma condition.
6. The method as recited in claim 5 , wherein the plasma condition includes a HBr/O 2 reactive ion etch.
7. The method as recited in claim 5 , wherein the plasma condition smooths a surface of the dielectric layer in the second region.
8. The method as recited in claim 1 , wherein the step of damaging the dielectric layer in the second region to provide an altered layer includes the step of illuminating the dielectric layer in the second region with radiation.
9. The method as recited in claim 8 , wherein the radiation includes ultraviolet radiation.
10. The method as recited in claim 1 , wherein the step of wet etching the dielectric layer includes the step of etching with hydrofluoric acid.
11. A method for forming dielectric protection in different regions of a semiconductor device comprising the steps of: forming structures in a first region and a second region; growing a first dielectric layer on surfaces of the structures and in between the structures in the first region and the second region; damaging the first dielectric layer in the second region without removing the first dielectric layer to provide an altered layer which is etchable at a faster rate than the first dielectric layer in the first region; wet etching the first dielectric layer in the first region to provide a first thickness in the first region and etching the altered layer to remove the altered layer from the second region; and growing a second dielectric layer having a second thickness in the second region such that the first region includes the first thickness of the first dielectric layer and the second thickness of the second dielectric layer.
12. The method as recited in claim 11 , wherein the first region is an array region and the second region is a support region.
13. The method as recited in claim 11 , wherein the first dielectric layer and the second dielectric layer include an oxide layer.
14. The method as recited in claim 11 , wherein the step of damaging the first dielectric layer in the second region to provide an altered layer includes the step of exposing the first dielectric layer in the second region to a plasma condition.
15. The method as recited in claim 14 , wherein the plasma condition includes a HBr/O 2 reactive ion etch.
16. The method as recited in claim 14 , wherein the plasma condition smooths a surface of the first dielectric layer in the second region.
17. The method as recited in claim 11 , wherein the step of damaging the first dielectric layer in the second region to provide an altered layer includes the step of illuminating the first dielectric layer in the second region with radiation.
18. The method as recited in claim 17 , wherein the radiation includes ultraviolet radiation.
19. The method as recited in claim 11 , wherein the step of wet etching includes the step of etching with hydrofluoric acid.
20. A method for forming protective oxides in an array region and a support region of a semiconductor memory comprising the steps of: providing a semiconductor substrate having a gate oxide layer formed thereon; patterning gate stacks in the support region and in the array region; oxidizing the gate stacks and the gate oxide layer to form a sidewall oxide on lateral surfaces of the gate stacks and increase a thickness of the gate oxide layer between the gate stacks; forming a resist over the array region; damaging the sidewall oxide and the gate oxide layer in the support region without removing the sidewall oxide and the gate oxide layer to provide an altered layer which is etchable at a faster rate than the sidewall oxide and the gate oxide layer in the array region; removing the resist; and wet etching the sidewall oxide and the gate oxide layer in the array region and the altered layer in the support region to provide a dielectric protection layer having a first thickness in the array region and a second thickness in the support region.
21. The method as recited in claim 20 , wherein the first thickness is greater than the second thickness.
22. The method as recited in claim 20 , wherein the step of damaging the sidewall oxide and the gate oxide layer in the support region to provide an altered layer includes the step of exposing the sidewall oxide and the gate oxide layer in the support region to a plasma condition.
23. The method as recited in claim 22 , wherein the plasma condition includes a HBr/O 2 reactive ion etch.
24. The method as recited in claim 22 , wherein the plasma condition smooths a surface of the sidewall oxide and the gate oxide layer in the support region.
25. The method as recited in claim 1 , wherein the step of damaging the sidewall oxide and the gate oxide layer in the support region to provide an altered layer includes the step of illuminating the sidewall oxide and the gate oxide layer in the support region with radiation.
26. The method as recited in claim 25 , wherein the radiation includes ultraviolet radiation.
27. The method as recited in claim 20 , wherein the step of wet etching includes the step of etching with hydrofluoric acid.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 26, 1999
March 5, 2002
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