A memory chip containing a dual bank memory system is arranged to be mounted cross-wise in its package with the major axis of the memory chip extending along the minor axis of the package. The data output register and the chip bond pads are located between the two memory banks so that the data read/write lines extend only through a portion of the memory chip to the data output register. All of the address chip bond pads are located in one row and all of the data chip bond pads are located in another row that extends in parallel with the row of address chip bond pads. Also, the column decoder circuit for each memory bank is located at the center of the memory bank. This allows the column select lines to be segmented into two groups, with one group of column select lines extending from the center of the memory array outwardly toward one side of the memory array and with the other group of column select lines extending from the center of the memory array outwardly toward opposite side of the memory array. The memory architecture and layout provided by the invention reduces the length of the data read/write lines and the column select lines, with an attendant reduction in the RC time constant, allowing reduction in the memory access times.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory chip comprising: a substrate; a first memory bank fabricated on the substrate; a second memory bank fabricated on the substrate, spaced apart from the first memory bank defining a chip bond pad region for the memory chip; a data output register fabricated on the substrate in the chip bond pad region between the first and second memory banks; a plurality of chip bond pads located in the chip bond pad region between the first and second memory banks and adjacent to the data output register; a first plurality of data read/write lines extending from the first memory bank to the data output register; and a second plurality of data read/write lines extending from the second memory bank to the data output register.
2. The memory chip according to claim 1 , including a first row of chip bond pads extending between first and second sides of the chip, and a second row of chip bond pads extending between the first and second sides of the chip, and wherein all of the address inputs of the device are connected to chip bond pads in said first row of chip bond pads, and wherein all of the data inputs/outputs of the memory are connected to chip bond pads located in said second row of chip bond pads.
3. The memory chip according to claim 2 , wherein the first row of chip bond pads extend in parallel with the second row of chip bond pads between the first and second memory banks.
4. A semiconductor memory chip comprising: a substrate; a first memory bank fabricated on the substrate; a first column decoder located within the first memory bank; a second memory bank fabricated on the substrate, spaced apart from the first memory bank defining a chip bond pad region for the memory chip; a second column decoder located within the second memory bank; a data output register fabricated on the substrate in the chip bond pad region between the first and second memory banks; a plurality of chip bond pads located in the chip bond pad region between the first and second memory banks and adjacent to the data output register; a first plurality of data read/write lines extending from the first memory bank to the data output register; and a second plurality of data read/write lines extending from the second memory bank to the data output register.
5. The memory chip according to claim 4 , including a first row of chip bond pads extending between first and second sides of the chip, and a second row of chip bond pads extending between the first and second sides of the chip, and wherein all of the address inputs of the device are connected to chip bond pads in said first row of chip bond pads, and wherein all of the data inputs/outputs of the memory are connected to chip bond pads located in said second row of chip bond pads.
6. The memory chip according to claim 5 , wherein the first row of chip bond pads extend in parallel with the second row of chip bond pads between the first and second memory banks.
7. A semiconductor memory chip comprising: a substrate; a pair of memory banks fabricated on the substrate defining a chip bond pad region between the pair of memory banks, wherein at least one of the banks comprises: a first group of sub-arrays; a second group of sub-arrays; a column decoder interposed between the first and second group of sub-arrays; a data output register fabricated on the substrate in the chip bond pad region between the first and second memory banks; a plurality of chip bond pads located in the chip bond pad region between the first and second memory banks and adjacent to the data output register; a first plurality of data read/write lines extending from the first memory bank to the data output register; and a second plurality of data read/write lines extending from the second memory bank to the data output register.
8. The memory chip according to claim 7 , including a first row of chip bond pads extending between first and second sides of the chip, and a second row of chip bond pads extending between the first and second sides of the chip, and wherein all of the address inputs of the device are connected to chip bond pads in said first row of chip bond pads, and wherein all of the data inputs/outputs of the memory are connected to chip bond pads located in said second row of chip bond pads.
9. The memory chip according to claim 8 , wherein the first row of chip bond pads extend in parallel with the second row of chip bond pads between the first and second memory banks.
10. An integrated circuit assembly comprising: an elongated memory chip, the memory chip having a major axis and a minor axis, the chip comprising: a substrate; a first memory bank fabricated on the substrate; a second memory bank fabricated on the substrate, spaced apart from the first memory bank defining a chip bond pad region for the memory chip; a data output register fabricated on the substrate in the chip bond pad region between the first and second memory banks; a plurality of chip bond pads located in the chip bond pad region between the first and second memory banks and adjacent to the data output register; a first plurality of data read/write lines extending from the first memory bank to the data output register; a second plurality of data read/write lines extending from the second memory bank to the data output register; and an elongated package for mounting the memory chip, the package having a major axis and a minor axis, and a plurality of pins, wherein the memory chip is oriented with its major axis extending along the minor axis of the package, and the plurality of chip bond pads are connected to thee plurality of pins.
11. The integrated circuit assembly of claim 10 , wherein the plurality of pins comprises a plurality of data pins and a plurality of address pins.
12. The integrated circuit assembly of claim 11 , wherein the plurality of chip bond pads includes a first row of chip bond pads extending between first and second sides of the chip, and a second row of chip bond pads extending between the first and second sides of the chip, and wherein all of the address pins are connected to chip bond pads in said first row of chip bond pads, and wherein all of the data pins are connected to chip bond pads located in said second row of chip bond pads.
13. The integrated circuit assembly of claim 12 , wherein the first row of chip bond pads extend in parallel with the second row of chip bond pads between the first and second memory banks.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 27, 2000
March 5, 2002
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