A memory device has an open-array architecture that includes alternate digit lines in the end subarrays that are not normally coupled to a sense amplifier. These digit lines are not normally coupled to a sense amplifier because there is no adjacent subarray containing digit lines that could be coupled to the other input of the sense amplifier. A sense amplifier is provided for each of these normally unused digit lines, and each normally unused digit line is coupled to one of the imports of a respective sense amplifier. The other input of each sense amplifier is coupled to a dummy load that is provided to simulate the resistance and capacitance of an actual digit line. The dummy load has a capacitance that may be adjusted so that the capacitance at both inputs to each sense amplifier are substantially equal. As a result, normally unused digit lines in the end subarray of a memory array, as well as the memory cells coupled to the digit lines, may be used.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory array comprising: a plurality of sub-arrays, each sub array including a plurality of memory cells arranged in rows and columns; a digit line for each column of each sub-array; a plurality of sense amplifiers, the digit lines and sense amplifiers being arranged in an open-array architecture so that each of a first plurality of sense amplifiers is coupled to a digit line in each of two adjacent sub-arrays except for a first set of digit lines in at least one end sub-array; a second plurality of sense amplifiers each having first and second complimentary inputs, the digit lines in the first set being coupled to the first input of a respective sense amplifier in the second plurality of sense amplifiers; and a load circuit coupled to the second input of each sense amplifier in the second plurality, the load circuit having an adjustable impedance.
2. The memory array of claim 1 wherein the load circuit comprises a circuit having an input terminal with an adjustable capacitance.
3. The memory array of claim 1 wherein the load circuit comprises a plurality of capacitors.
4. The memory array of claim 3 wherein each of the capacitors is coupled to the second input of each sense amplifier by a respective MOSFET transistor.
5. The memory array of claim 3 wherein each of the capacitors comprise a memory cell capacitor.
6. The memory array of claim 3 wherein plurality of MOSFETs coupled to respective ones of the capacitors have respective control terminals that are coupled to each other.
7. The memory array of claim 1 wherein the load circuit comprises a plurality of series circuits connected in parallel with each other, each of the series circuits comprising a transistor in series with a capacitive device.
8. The memory array of claim 1 wherein the load circuits comprise: a plurality of access transistors coupled to the second input of each sense amplifier in the second plurality; a plurality of word lines, each of the word lines being coupled to the gates of a plurality of correspondingly positioned access transistors for a plurality of sense amplifiers; a memory cell capacitor coupled to each of the access transistors so that the memory cell capacitor is coupled to one of the sense amplifiers when the transistor is conductive; and a control circuit for applying a signal to one or a plurality of word lines to couple one or a plurality of the memory cell capacitors to the second input of each sense amplifier in the second plurality.
9. A memory array comprising: a first plurality of sense amplifiers and digit lines arranged in an open array architecture, each digit line in the array except for a set of digit lines at an end of the array being coupled to a first input of a respective sense amplifier, a second input of the sense amplifier being coupled to an adjacent digit line; a plurality of adjustable load circuits; and a second plurality of sense amplifiers each having a first input coupled to a respective one of the digit lines at the end of the array and a second input coupled to a respective one of the load circuits.
10. The memory array of claim 9 wherein each of the adjustable load circuits comprises a circuit having an input terminal with an adjustable capacitance.
11. The memory array of claim 9 wherein each of the load circuits comprises a plurality of capacitors.
12. The memory array of claim 9 wherein each of the capacitors is coupled to the second input of each sense amplifier by a respective MOSFET transistor.
13. The memory array of claim 11 wherein each of the capacitors comprises a memory cell capacitor.
14. The memory device of claim 13 wherein a plurality of MOSFETs coupled to respective ones of the capacitors have respective control terminals that are coupled to each other.
15. The memory array of claim 9 wherein each of the load circuits comprises a plurality of series circuits connected in parallel with each other, each of the series circuits comprising a transistor in series with a capacitive device.
16. The memory array of claim 9 wherein the load circuits comprise: a plurality of access transistors coupled to the second input of each sense amplifier in the second plurality; a plurality of word lines, each of the word lines being coupled to the gates of a plurality of correspondingly positioned access transistors for a plurality of sense amplifiers; a memory cell capacitor coupled to each of the access transistors so that the memory cell capacitor is coupled to one of the sense amplifiers when the transistor is conductive; and a control circuit for applying a signal to one or a plurality of word lines to couple one or a plurality of the memory cell capacitors to the second input of each sense amplifier in the second plurality.
17. A memory device comprising: a memory array having a plurality of sub-arrays, each sub array including a plurality of memory cells arranged in rows and columns; a digit line for each column of each sub-array; a plurality of sense amplifiers, the digit lines and sense amplifiers being arranged in an open-array architecture so that each of a first plurality of sense amplifiers is coupled to a digit line in each of two adjacent sub-arrays except for a first set of digit lines in at least one end sub-array; a second plurality of sense amplifiers each having first and second complimentary inputs, the digit lines in the first set being coupled to the first input of a respective sense amplifier in the second plurality of sense amplifiers; a load circuit coupled to the second input of each sense amplifier in the second plurality of sense amplifiers, the load circuit having an adjustable impedance; an address decoder receiving a memory address at an external terminal, the address decoder being operable to activate a row and column in the array corresponding to the memory address; and a data path operable to couple read data from an external terminal to the memory array and write data from the memory array to the external terminal.
18. The memory device of claim 17 wherein the load circuit comprises a circuit having an input terminal with an adjustable capacitance.
19. The memory device of claim 17 wherein the load circuit comprises a plurality of capacitors.
20. The memory device of claim 19 wherein each of the capacitors is coupled to the second input of each sense amplifier by a respective MOSFET transistor.
21. The memory device of claim 19 wherein the capacitors comprise a memory cell capacitor.
22. The memory device of claim 19 wherein plurality of MOSFETs coupled to respective ones of the capacitors have respective control terminals that are coupled to each other.
23. The memory device of claim 17 wherein the load circuit comprises a plurality of series circuits connected in parallel with each other, each of the series circuits comprising a transistor in series with a capacitive device.
24. The memory device of claim 17 wherein the memory device comprises a dynamic random access memory.
25. The memory device of claim 24 wherein the dynamic random access memory device comprises a synchronous dynamic random access memory.
26. A memory device comprising: a memory array comprising: a first plurality of sense amplifiers and digit lines arranged in an open array architecture, each digit line in the array except for a set of digit lines at an end of the array being coupled to a first input of a respective sense amplifier, a second input of the sense amplifier being coupled to an adjacent digit line; a plurality of load circuits each having an adjustable impedance; and a second plurality of sense amplifiers each having a first input coupled to a respective one of the digit lines at the end of the array and a second input coupled to a respective one of the load circuits; an address decoder receiving a memory address at an external terminal, the address decoder being operable to activate a row and column in the array corresponding to the memory address; and a data path operable to couple read data from an external terminal to the memory array and write data from the memory array to the external terminal.
27. The memory device of claim 26 wherein each of the load circuits comprises a circuit having an input terminal with an adjustable capacitance.
28. The memory device of claim 26 wherein the load circuit comprises a plurality of capacitors.
29. The memory device of claim 28 wherein each of the capacitors is coupled to the second input of each sense amplifier by a respective MOSFET transistor.
30. The memory device of claim 28 wherein each of the capacitors comprises a memory cell capacitor.
31. The memory device of claim 28 wherein a plurality of MOSFETs coupled to respective ones of the capacitors have respective control terminals that are coupled to each other.
32. The memory device of claim 26 wherein each of the load circuits comprises a plurality of series circuits connected in parallel with each other, each of the series circuits comprising a transistor in series with a capacitive device.
33. The memory device of claim 26 wherein the memory device comprises a dynamic random access memory.
34. The memory device of claim 33 wherein the dynamic random access memory device comprises a synchronous dynamic random access memory.
35. A computer system comprising: a processor; a peripheral device bus; a memory device, comprising a memory array having a plurality of sub-arrays, each sub array including a plurality of memory cells arranged in rows and columns; a digit line for each column of each sub-array; a plurality of sense amplifiers, the digit lines and sense amplifiers being arranged in an open-array architecture so that each of a first plurality of sense amplifiers is coupled to a digit line in each of two adjacent sub-arrays except for a first set of digit lines in at least one end sub-array; a second plurality of sense amplifiers each having first and second complimentary inputs, the digit lines in the first set being coupled to the first input of a respective sense amplifier in the second plurality of sense amplifiers; a load circuit coupled to the second input of each sense amplifier in the second plurality of sense amplifiers, the load circuit having an adjustable impedance; an address decoder receiving a memory address at an external terminal, the address decoder being operable to activate a row and column in the array corresponding to the memory address; and a data path operable to couple read data from an external terminal to the memory array and write data from the memory array to the external terminal.
36. The computer system of claim 35 wherein the load circuit comprises a circuit having an input terminal with an adjustable capacitance.
37. The computer system of claim 35 wherein the load circuit comprises a plurality of capacitors.
38. The computer system of claim 37 wherein the resistive device comprises a MOSFET transistor biased to an ON condition.
39. The computer system of claim 37 each of the capacitors is coupled to the second input of each sense amplifier by a respective MOSFET transistor.
40. The computer system of claim 37 wherein each of the capacitors comprise a memory cell capacitor.
41. The computer system of claim 35 wherein the load circuit comprises a plurality of series circuits connected in parallel with each other, each of the series circuits comprising a transistor in series with a capacitive device.
42. The computer system of claim 35 wherein the memory device comprises a dynamic random access memory.
43. The computer system of claim 42 wherein the dynamic random access memory device comprises a synchronous dynamic random access memory.
44. A computer system comprising: a processor; a peripheral device bus; a memory device, comprising a memory array comprising: a first plurality of sense amplifiers and digit lines arranged in an open array architecture, each digit line in the array except for a set of digit lines at an end of the array being coupled to a first input of a respective sense amplifier, a second input of the sense amplifier being coupled to an adjacent digit line; a plurality of adjustable load circuits; and a second plurality of sense amplifiers each having a first input coupled to a respective one of the digit lines at the end of the array and a second input coupled to a respective one of the load circuits; an address decoder receiving a memory address at an external terminal, the address decoder being operable to activate a row and column in the array corresponding to the memory address; and a data path operable to couple read data from an external terminal to the memory array and write data from the memory array to the external terminal; a bus bridge coupling the processor to the memory device and the peripheral device bus; an input device coupled to the peripheral device bus; an output device coupled to the peripheral device bus; and a mass storage device coupled to the peripheral device bus.
45. The computer system of claim 44 wherein each of the load circuits comprises a circuit having an input terminal with an adjustable capacitance.
46. The computer system of claim 44 wherein the load circuit comprises a plurality of capacitors.
47. The computer system of claim 46 wherein each of the capacitors is coupled to the second input of each sense amplifier by a respective MOSFET transistor.
48. The computer system of claim 46 wherein each of the capacitors comprises a memory cell capacitor.
49. The computer system of claim 46 wherein plurality of MOSFETs coupled to respective ones of the capacitors have respective control terminals that are coupled to each other.
50. The computer system of claim 44 wherein each of the load circuits comprises a plurality of series circuits connected in parallel with each other, each of the series circuits comprising a transistor in series with a capacitive device.
51. The computer system of claim 44 wherein the memory device comprises a dynamic random access memory.
52. The computer system of claim 51 wherein the dynamic random access memory device comprises a synchronous dynamic random access memory.
53. In a memory array having an open array architecture in which a plurality of digit lines at the end of the array that are unconnected to a sense amplifier and are thus unused, a method of using the digit lines, comprising: coupling each of the digit lines to one input of a respective sense amplifier; and coupling a second input of the sense amplifier to a simulated capacitance.
54. The method of claim 53 , further comprising: testing the memory array to determine if each of two inputs to a sense amplifier have substantially the same capacitance; and adjusting the capacitance of the simulated capacitance based on the testing.
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December 7, 2000
March 12, 2002
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