In the emulation of a target system utilizing a multiprocessor (12) host system (10) with a longer word length than the target system, processor, memory, and cache overhead are minimized by utilizing a locked compare-exchange to update fill words in memory. The old contents of a word (48) in memory are loaded (80) into a first register (52). A loop is then entered. The contents of the first register (52) are copied (82) into a second (54). The contents of the second register (54) are then appropriately modified (84), depending on the instruction being emulated. After a lock (90), the two registers are compare-exchanged (86) with the memory word (48), resulting in the modified second register (54) being written to the memory word (48) if the contents of the first register (52) match. Otherwise, the compare-exchange instruction (86) loads the current copy of the word (48) into the first register (52), and the loop repeats.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of updating a designated memory location in a shared emulated memory when emulating a multiprocessor target system utilizing a multiprocessor host system operating on the shared emulated memory, said method comprising: A) loading an initial operand comprising an instruction for the multiprocessor target system into a first register; B) loading the initial operand from the first register into a second register; C) modifying the initial operand in the second register to form a modified operand; and utilizing a compare-exchange instruction: D) testing whether a contents of the designated memory location matches the initial operand in the first register; and E) writing the modified operand in the second register to the designated memory location if the contents of the designated memory location matches the initial operand.
2. The method in claim 1 which further comprises: F) repeating steps (A), (B), (C), (D), and (E) until the contents of the designated memory location matches the initial operand in the test in step (D).
3. The method in claim 2 wherein: step (F) is implemented utilizing a branch-on-condition-code instruction that branches based on a condition code set by the compare-exchange instruction.
4. The method in claim 2 which further comprises: G) guaranteeing atomicity of steps (D) and (E) by locking a bus before step (D).
5. The method in claim 4 wherein: the locking in step (G) operates by asserting a LOCK//signal when executing steps (D) and (E).
6. The method in claim 4 which further comprises: H) repeating steps (A), (B), (C), (D), (E), and (F) as a loop until the contents of the designated memory location matches the initial operand in the test in step (D).
7. The method in claim 1 which further comprises: G) prefetching the contents of the designated memory location into a cache memory before steps (D) and (E).
8. The method in claim 7 wherein: the prefetching in step (G) stores a value into a portion of the designated memory location unused in the target system.
9. The method in claim 7 wherein: the prefetching in step (G) utilizes an explicit cache prefetch instruction.
10. A host data processing system for emulating a multiprocessor target system, wherein the host data processing system comprises: a plurality of processors; a memory coupled to and shared among the plurality of processors; and a portion of a target system emulation software stored in a Computer Software Storage Medium for updating a designated memory location in the memory, said portion of the target system emulation software comprising: A) a set of computer instructions stored in a Computer Software Storage Medium for loading an initial operand into a first register, which initial operand comprises an instruction for the multiprocessor target system; B) a set of computer instructions stored in a Computer Software Storage Medium for loading the initial operand from the first register into a second register; C) a set of computer instructions stored in a Computer Software Storage Medium for modifying the initial operand in the second register to form a modified operand; D) a set of computer instructions stored in a Computer Software Storage Medium for testing whether a contents of the designated memory location matches the initial operand in the first register; and E) a set of computer instructions stored in a Computer Software Storage Medium for writing the modified operand in the second register to the designated memory location if the contents of the designated memory location matches the initial operand; wherein sets (C) and (D) are implemented together as a common set and comprise a compare-exchange instruction.
11. The host data processing system in claim 10 which further comprises: F) a set of computer instructions stored in a Computer Software Storage Medium for repeating sets (A), (B), (C), (D), and (E) of computer instructions as a loop until the contents of the designated memory location matches the initial operand as a result of the testing in set (D) of computer instructions.
12. The host data processing system in claim 11 wherein: set (F) of computer instructions comprises: a branch-on-condition-code instruction that branches based on a condition code get by the compare-exchange instruction.
13. The host data processing system in claim 11 which further comprises: G) a set of computer instructions stored in a Computer Software Storage Medium for guaranteeing uninterrupted execution of sets (D) and (E) of computer instructions by locking a bus before executing sets (D) and (E) of computer instructions.
14. The host data processing system in claim 13 wherein: set (G) of computer instructions comprises: a lock function that operates by asserting a LOCK//signal when executing sets (D) and (E) of computer instructions.
15. The host data processing system in claim 13 which further comprises: H) a set of computer instructions stored in a Computer Software Storage Medium for repeating sets (A), (B), (C), (D), (E), and (F) of computer instructions as a loop until the contents of the designated memory location matches the initial operand as a result of the testing in set (D) of computer instructions.
16. The host data processing system in claim 10 which further comprises: G) a set of computer instructions stored in a Computer Software Storage Medium for prefetching the contents of the designated memory location into a cache memory before executing sets (D) and (E) of computer instructions.
17. The host data processing system in claim 16 wherein: set (G) of computer instructions comprises: a store instruction for storing a value into a portion of the designated memory location unused in the target system.
18. The host data processing system in claim 16 wherein get (G) of computer instructions comprises: an explicit cache prefetch instruction.
19. A computer readable Non-Volatile Storage Medium encoded with an emulation software program for emulating a multiprocessor target system on a multiprocessor host system operating on a shared emulated memory, wherein a portion of the emulation software program for updating a designated memory location in the shared emulated memory comprises: A) a set of computer instructions for loading an initial operand into a first register, which initial operand comprises an instruction for the multiprocessor target system; B) a set of computer instructions for loading the initial operand from the first register into a second register; C) a set of computer instructions for modifying the initial operand in the second register to form a modified operand; D) a set of computer instructions for testing whether a contents of the designated memory location matches the initial operand in the first register; E) a set of computer instructions for writing the modified operand in the second register to the designated memory location if the contents of the designated memory location matches the initial operand; and F) a set of computer instructions for repeating sets (A), (B), (C), (D), and (E) of computer instructions as a loop until the contents of the designated memory location matches the initial operand as a result of the testing in set (D) of computer instructions; wherein sets (C) and (D) are implemented together as a common set and comprise a compare-exchange instruction.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 8, 1998
March 19, 2002
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