A first-in-first-out (FIFO) entry point circuit for a network interface card. The novel circuit of the present invention provides a FIFO entry point circuit within a network interface card (NIC). The FIFO implementation allows multiple downlist pointers to be maintained within the transmit (Tx) FIFO entry point circuit and also allows multiple uplist pointers to be maintained for the receive (Rx) FIFO entry point circuit. For the Tx FIFO entry point circuit, only one register is visible to the processor which can load a memory pointer into the entry point thereby placing the memory pointer on the bottom on the FIFO. Only one register is seen for the Rx FIFO entry point circuit. With respect to the Tx FIFO entry point circuit, the NIC takes the oldest entry, obtains the packet from memory that is indicated by the corresponding pointer and transmits the packet onto a network. If the packet points to a next packet, then that next packet is sent, otherwise the next pointer of the Tx FIFO entry point is then processed by the NIC. Signals indicate when the Rx or Tx FIFO entry points are full. An analogous process operates for the Rx FIFO entry point. Providing a queued entry point reduces processor utilization and PCI bus utilization in communicating packets with the network because memory pointers can be directly pushed onto the transmit FIFO by the processor without encountering race conditions. Providing a queued entry point also increases NIC efficiency by avoiding processor initiated NIC stalls. Both improve quality of service performance.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A network adapter card (NIC) for coupling with a computer system having a processor and a memory unit, said NIC comprising: a queued transmit entry point circuit comprising a transmit entry point register and a plurality of memory cells configured as a first-in-first-out (FIFO) memory circuit, said transmit entry point register for receiving new data packet pointers from said processor and for queuing said new data packet pointers into said FIFO memory circuit, said transmit entry point register for maintaining the oldest queued data packet pointer of said queued transmit entry point circuit; a transmit FIFO memory circuit for containing digital data to be transmitted onto a network; and a control circuit for accessing digital data from a memory space of said memory unit of said computer system and for supplying said digital data to said transmit FIFO memory circuit, said memory space being identified by said oldest queued data packet pointer as maintained by said transmit entry point register.
2. A network adapter card as described in claim 1 wherein said transmit entry point register is the only memory cell of said queued transmit entry point circuit that is visible to said processor.
3. A network adapter card as described in claim 1 wherein said queued transmit entry point circuit supplies said control circuit with a next-in-order data packet pointer upon completion of the most recently transmitted data packet.
4. A network adapter card as described in claim 1 further comprising an overflow circuit for generating a FIFO full signal for said processor when said queued transmit entry point circuit is full.
5. A network adapter card as described in claim 1 further comprising: a receive FIFO memory circuit for receiving digital data from said network; and a queued receive entry point circuit comprising a receive entry point register and a plurality of memory cells configured as a FIFO memory circuit, said receive entry point register for receiving new memory space pointers and for queuing said new memory space pointers into said FIFO memory circuit of said queued receive entry point circuit, said receive entry point register for maintaining the oldest queued memory space pointer of said queued receive entry point circuit; and wherein said control circuit is also for storing digital data from said receive FIFO memory circuit to said memory unit of said computer system at a memory space indicated by said memory space pointer maintained by said FIFO receive entry point register.
6. A computer system comprising: a processor coupled to a bus; a memory unit coupled to said bus; and a network adapter card coupled to said bus wherein said network adapter card comprises: a queued transmit entry point circuit comprising a transmit entry point register and a plurality of memory cells configured as a first-in-first-out (FIFO) memory circuit, said transmit entry point register for receiving new data packet pointers from said processor and for queuing said new data packet pointers into said FIFO memory circuit, said transmit entry point register for maintaining the oldest queued data packet pointer of said queued transmit entry point circuit; a transmit FIFO memory circuit for containing digital data to be transmitted onto a network; and a control circuit for accessing digital data from a memory space of said memory unit of said computer system and for supplying said digital data to said transmit FIFO memory circuit, said memory space being identified by said oldest queued data packet pointer as maintained by said transmit entry point register.
7. A computer system as described in claim 6 wherein said transmit entry point register is the only memory cell of said queued transmit entry point circuit that is visible to said processor.
8. A computer system as described in claim 6 wherein said queued transmit entry point circuit supplies said control circuit with a next-in-order data packet pointer upon completion of the most recently transmitted data packet.
9. A computer system as described in claim 6 further comprising an overflow circuit for generating a FIFO full signal for said processor when said queued transmit entry point circuit is full.
10. A computer system as described in claim 6 wherein said network interface card further comprises: a receive FIFO memory circuit for receiving digital data from said network; and a queued receive entry point circuit comprising a receive entry point register and a plurality of memory cells configured as a FIFO memory circuit, said receive entry point register for receiving new memory space pointers and for queuing said new memory space pointers into said FIFO memory circuit of said queued receive entry point circuit, said receive entry point register for maintaining the oldest queued memory space pointer of said queued receive entry point circuit; and wherein said control circuit is also for storing digital data from said receive FIFO memory circuit to said memory unit of said computer system at a memory space indicated by said memory space pointer maintained by said FIFO receive entry point register.
11. A computer system as described in claim 6 wherein said bus is compliant with the Peripheral Components Interconnect (PCI) bus standard.
12. A computer system as described in claim 6 wherein said memory unit is a volatile memory unit.
13. A computer system as described in claim 6 wherein said network is substantially compliant with the Ethernet communication standard.
14. A computer system as described in claim 6 wherein said network is substantially compliant with the IEEE 1394 communication standard.
15. A computer system as described in claim 6 wherein said network is substantially compliant with the Home PhoneLine standard.
16. A computer system as described in claim 6 wherein said network is substantially compliant with the HomeRF standard.
17. A computer system as described in claim 6 wherein said network is substantially compliant with the Home PowerLine standard.
18. In a computer system having a processor, a memory unit and a network interface card (NIC), a method for queuing the transmission of a memory stored data packet over a network, said method comprising the steps of: a) said processor requesting access to said bus; b) said processor receiving a grant of access to said bus; and c) said processor queuing said data packet to be transmitted by said NIC without stalling said NIC, said step c) performed by said processor supplying a data packet pointer to a transmit entry point register of said NIC, wherein said data packet pointer indicates a memory space within said memory unit that contains said data packet, and wherein said NIC comprises a queued transmit entry point circuit comprising a transmit entry point register and a plurality of memory cells configured as a first-in-first-out (FIFO) memory circuit; d) said transmit entry point register receiving new data packet pointers from said processor and queuing said new data packet pointers into said FIFO memory circuit; and e) said transmit entry point register maintaining the oldest queued data packet pointer of said queued transmit entry point circuit.
19. A method as described in claim 18 wherein said NIC further comprises: a transmit FIFO memory circuit for containing digital data to be transmitted onto a network; and a control circuit for accessing digital data from a memory space of said memory unit of said computer system, said memory space being identified by a data packet pointer maintained by said transmit entry point register; and wherein said method further comprises the steps of: f) said control circuit supplying digital data to said transmit FIFO memory circuit; and g) said queued transmit entry point circuit supplying said control circuit with a next-in-order data packet pointer upon completion of the most recently transmitted data packet.
20. A method as described in claim 18 further comprising the step of generating a FIFO full signal for said processor when said FIFO transmit entry point circuit is full.
21. A method as described in claim 18 wherein said network is substantially compliant with the Ethernet communication standard.
22. A method as described in claim 18 wherein said network is substantially compliant with the IEEE 1394 communication standard.
23. A method as described in claim 18 wherein said network is substantially compliant with the Home PhoneLine standard.
24. A method as described in claim 18 wherein said network is substantially compliant with the HomeRF standard.
25. A method as described in claim 18 wherein said network is substantially compliant with the Home PowerLine standard.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 27, 1999
March 19, 2002
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