A CMOS memory device includes source and drain regions diffused into a substrate, a polysilicon gate structure formed over a channel region located between the first and second diffusion regions, and a pre-metal dielectric structure formed over the polysilicon gate structure. The pre-metal dielectric structure is a triple layer structure including a lower Borophosphosilicate glass (BPSG) layer formed over the polysilicon gate structure, a Nitride layer formed on the lower BPSG layer, and an upper dielectric layer (e.g., BPSG or USG) formed on the Nitride layer. The Phosphorous concentration in the lower BPSG layer is greater than the Phosphorous concentration in the upper dielectric layer, thereby providing retention protection for the underlying memory structures while facilitating optimal chemical mechanical polishing (CMP) planarization characteristics. The Nitride layer acts as a barrier to impede the migration of Phosphorous from the lower BPSG layer to the upper dielectric layer, and to prevent the migration of impurities from the upper dielectric layer to the lower dielectric layer that are introduced during CMP planarization.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A dielectric structure for a CMOS memory device, the CMOS memory device including a memory structure, the dielectric structure comprising: a lower dielectric layer formed over the memory structure, the lower dielectric layer having a first doping concentration; an intermediate isolation layer formed on the lower dielectric layer, and an upper dielectric layer formed on the intermediate isolation layer, the upper dielectric layer having a second doping concentration; wherein the first doping concentration of the lower dielectric layer is greater than the second doping concentration of the upper dielectric layer, and wherein the intermediate isolation layer includes a material that impedes migration of the dopant from the lower dielectric layer to the upper dielectric layer.
2. The dielectric structure according to claim 1 , wherein the lower dielectric layer consists essentially of Borophosphosilicate glass (BPSG), and wherein a ratio of Boron to Phosphorous in the lower dielectric layer is 3:8.
3. The dielectric structure according to claim 2 , wherein the lower layer has a thickness in the range of 2000 to 6000 .
4. The dielectric structure according to claim 1 , wherein the upper dielectric layer consists essentially of Borophosphosilicate glass (BPSG), and wherein a ratio of Boron to Phosphorous in the upper dielectric layer is 2:4.
5. The dielectric structure according to claim 4 , wherein the upper dielectric layer has a thickness in the range of 5000 to 12000 .
6. The dielectric structure according to claim 1 , wherein both the lower dielectric layer and the upper dielectric layer consist essentially of Borophosphosilicate glass (BPSG), and wherein the concentration of Phosphorous in the lower dielectric layer is in the range of 7 to 9 weight percent, and the concentration of Phosphorous in the upper dielectric layer is in the range of 3 to 5 weight percent.
7. The dielectric structure according to claim 1 , wherein the upper layer comprises Tetraethyl Orthosilicate (TEOS).
8. The dielectric structure according to claim 1 , wherein the intermediate isolation layer comprises a Nitride film having a thickness in the range of 100 to 300 .
9. The dielectric structure according to claim 1 , further comprising: a lower Nitride film formed on the memory structure; and an undoped silicon glass layer formed between the lower Nitride layer and the lower dielectric layer.
10. The dielectric structure according to claim 9 , wherein the lower Nitride film has a thickness in the range of 100 to 300 ; and wherein the undoped silicon glass layer has a thickness in the range of 500 to 1500 .
11. A CMOS device comprising: a substrate; first and second diffusion regions formed in the substrate; a polysilicon gate structure formed over a channel region of the substrate, the channel region being located between the first and second diffusion regions; and a pre-metal dielectric structure formed over the polysilicon gate structure and the first and second diffusion regions, the pre-metal dielectric structure including: a lower Borophosphosilicate glass (BPSG) layer formed on an upper surface of the polysilicon gate structure, an intermediate Nitride layer formed on the lower BPSG layer, and an upper dielectric layer formed on the intermediate Nitride layer; wherein a concentration of Phosphorous in the lower BPSG layer is greater than a concentration of Phosphorous in the upper dielectric layer.
12. The CMOS device according to claim 11 , further comprising: a lower Nitride layer formed on the polysilicon gate structure; and an undoped silicon glass layer formed between the Nitride layer and the lower BPSG layer.
13. The CMOS device according to claim 11 , wherein the upper dielectric layer consists essentially of Borophosphosilicate glass (BPSG), and wherein the concentration of Phosphorous in the lower BPSG layer is in the range of 7 to 9 weight percent, and the concentration of Phosphorous in the upper dielectric layer is in the range of 3 to 5 weight percent.
14. A method of fabricating a CMOS device, the method comprising: forming a memory structure on a substrate; forming a lower dielectric layer over the memory structure, the lower dielectric layer having a first doping concentration; forming an intermediate isolation layer on the lower dielectric layer; forming an upper dielectric layer on the intermediate isolation layer, the upper dielectric layer having a second doping concentration that is less than the first doping concentration; and planarizing the upper dielectric layer using a chemical mechanical polishing process.
15. The method according to claim 14 , wherein the step of forming the lower dielectric layer comprises forming a layer of Borophosphosilicate glass (BPSG) having a Boron-to-Phosphorous ratio of 3:8.
16. The method according to claim 14 , wherein the step of forming the intermediate isolation layer comprises forming a Nitride film having a thickness in the range of 100 to 300 .
17. The method according to claim 14 , wherein the step of forming the upper dielectric layer comprises forming a layer of Borophosphosilicate glass (BPSG) having a Boron-to-Phosphorous ratio of 2:4.
18. The method according to claim 14 , wherein the step of forming the upper dielectric layer comprises forming Tetraethyl Orthosilicate (TEOS).
19. The method according to claim 14 , further comprising: forming a lower Nitride film on the memory structure; and forming an undoped silicon glass layer on the Nitride film such that the undoped silicon glass layer is sandwiched between the Nitride layer and the lower dielectric layer.
20. The method according to claim 14 , further comprising forming a metal conductor on a planarized upper surface of the upper dielectric layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 3, 2000
March 26, 2002
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