A method is provided for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin. According to the method, a single pin is enabled to receive trimming data by biasing the pin to outside its operating range. A clock signal is obtained from a division of the bias potential of the pin, and the logic value of the trimming data is obtained from a different division of the bias potential of the pin. Serial acquisition of the data is enabled in accordance with the clock signal, and the data is transferred to the modification circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin, said method comprising the steps of: enabling a single pin to receive trimming data by biasing the pin to outside its operating range; obtaining a clock signal from a division of the bias potential of the pin; obtaining the logic value of the trimming data from a different division of the bias potential of the pin; enabling serial acquisition of the data in accordance with the clock signal; transferring the data to the modification circuit.
2. The method according to claim 1 , further comprising the step of transferring the data to selection logic with the modification circuit bypassed on the occurrence of a simulated trimming operation.
3. The method according to claim 1 , wherein the transfer operation is earned out using a shift register.
4. The method according to claim 3 , further comprising the step of supplying the shift register with the data on one input and the clock signal on another input.
5. The method according to claim 1 , wherein the step of obtaining a clock signal includes the sub-step of comparing a division of the bias potential on the pin with a reference potential.
6. The method according to claim 1 , wherein the step of obtaining the logic value of the trimming data includes the sub-step of comparing a division of the bias potential on the pin with a reference potential.
7. The method according to claim 1 , wherein the step of obtaining a clock signal includes the sub-step of comparing a division of the bias potential on the pin with a reference potential, the step of obtaining the logic value of the trimming data includes the sub-step of comparing a division of the bias potential on the pin with a reference potential, and the trimming data logic value comparison threshold is higher than the comparison threshold used to obtain the clock signal.
8. An electronic circuit for carrying out a trimming operation on circuit portions of an integrated circuit having at least a first input or supply pin, an output pin, and a second supply pin, the circuit comprising: memory elements; means for modifying the state of the memory elements; and first and second comparators having their inputs connected to a trimming pin to produce a clock signal for the trimming operation and a sequence of trimming data, wherein a single trimming pin is used.
9. The circuit according to claim 8 , wherein the first comparator has an input coupled to the trimming pin via a voltage divider, and the second comparator has an input coupled to the trimming pin via a different node of the voltage divider.
10. The circuit according to claim 9 , further comprising a shift register connected downstream of the first and second comparators.
11. The circuit according to claim 10 , wherein the shift register is of the n 2 order.
12. The circuit according to claim 10 , wherein the means of modifying is connected downstream of the shift register.
13. The circuit according to claim 10 , wherein the shift register receives trimming data on one input from the output of the second comparator, and receives a clock signal on another input from the output of the first comparator.
14. The circuit according to claim 10 , wherein the shift register has its output connected to selection logic so as to bypass the means of modifying on the occurrence of a simulation of the trimming results.
15. The circuit according to claim 14 , further comprising a multiplexer coupled between the outputs of the shift register and the selection logic.
16. The circuit according to claim 15 , wherein an n-th output of the shift register is connected to an input of the multiplexer to select a simulated trimming operation.
17. The circuit according to claim 14 , wherein the selection logic has its output connected to a voltage reference of the circuit portion producing a reference voltage signal for the integrated circuit.
18. The circuit according to claim 14 , wherein the memory elements are coupled between the outputs of the shift register and the selection logic.
19. The circuit according to claim 15 , wherein the memory elements arc coupled between the outputs of the shift register and the selection logic.
20. An information processing system including at least one electronic circuit for carrying out a trimming operation on circuit portions of an integrated circuit having at least a first input or supply pin, an output pin, and a second supply pin, the circuit comprising: memory elements; means for modifying the state of the memory elements; and first and second comparators having their inputs connected to a trimming pin to produce a clock signal for the trimming operation and a sequence of trimming data, wherein a single trimming pin is used.
21. The information processing system according to claim 20 , wherein the first comparator has an input coupled to the trimming pin via a voltage divider, and the second comparator has an input coupled to the trimming pin via a different node of the voltage divider.
22. The information processing system according to claim 21 , further comprising a shift register connected downstream of the first and second comparators.
23. The information processing system according to claim 20 , further comprising a shift register that receives trimming data on one input from the output of the second comparator, and receives a clock signal on another input from the output of the first comparator.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 26, 2001
April 2, 2002
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