A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can detect a brown-out of a supply voltage. The memory device comprises a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value. A latch is coupled to the voltage detection circuit and can be programmed to indicate if the supply voltage dropped below the predetermined value. An external controller can read a status of the latch. The memory, therefore, can provide an indication to an external controller that a reset, or initialization, operation is needed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A flash memory device comprising: a power supply input connection; a voltage comparator to compare a voltage provided on the power supply input connection to a reference voltage; and a programmable storage circuit to indicate if the voltage on the power supply input is greater than or less than the reference voltage.
2. The system of claim 1 wherein the flash memory comprising a package having a plurality of interconnects arranged in a pattern compatible with a synchronous dynamic random access memory (SDRAM).
3. The flash memory device of claim 1 further comprising output circuitry to provide data from the storage circuit in response to a status inquiry.
4. The flash memory device of claim 1 further comprising an initialize circuit to store first default data in the storage circuit upon applying power to the flash memory device.
5. The flash memory device of claim 1 comprising a clock signal input connection, wherein the flash memory device is a synchronous memory.
6. The flash memory device of claim 5 further comprising: a write enable connection (WE ) to receive a write enable signal; a column address strobe connection (CAS ) to receive a column address strobe signal; a row address strobe connection (RAS ) to receive a row address strobe signal; and a chip select connection (CS ) to receive a chip select signal.
7. The flash memory device of claim 5 further comprising: an array of non-volatile memory cells; and a plurality of external connections comprising, a plurality of bi-directional data connections, a plurality of memory address connections, a write enable connection, a column address strobe connection, and a row address strobe connection.
8. The flash memory device of claim 5 wherein the plurality of external connections further comprises: a clock enable connection, a chip select connection, a plurality of memory array bank address connections, power supply connections, a plurality of data mask connections, and a reset connection.
9. The flash memory device of claim 1 further comprising a package having a plurality of interconnect pins corresponding to the external connections, wherein the interconnect pins are physically arranged in a pattern compatible with a synchronous dynamic random access memory (SDRAM).
10. A memory device comprising: a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value; and a brown-out latch circuit programmable to a first data state after an initialization operation is performed, the brown-out latch is programmable to a second state in response to the voltage detection circuit.
11. The memory device of claim 10 wherein the second state indicates that the supply voltage dropped below the predetermined value.
12. The memory device of claim 10 further comprising an externally accessible status register to provide data indicating a programmed state of the brown-out latch.
13. The memory device of claim 12 wherein the predetermined value is about one volt below a normal supply voltage, Vcc.
14. The memory device of claim 12 wherein a nominal supply voltage is about 3 volts and the predetermined value is about 2 volts.
15. A flash memory comprising: a voltage supply detection circuit; and a status register to provide output data indicating a status of a supply voltage relative to a reference voltage level.
16. The flash memory of claim 15 further comprising output circuitry to provide data from the status register in response to a status inquiry.
17. The flash memory of claim 15 further comprising an initialize circuit to store first default data in a storage circuit upon applying power to the flash memory device.
18. The flash memory of claim 15 comprising a clock signal input connection, wherein the flash memory is a synchronous memory.
19. The flash memory of claim 15 further comprising: a write enable connection (WE ) to receive a write enable signal; a column address strobe connection (CAS ) to receive a column address strobe signal; a row address strobe connection (RAS ) to receive a row address strobe signal; and a chip select connection (CS ) to receive a chip select signal.
20. The flash memory of claim 15 further comprising a package having a plurality of interconnects corresponding to the external connections, wherein the interconnects are physically arranged in a pattern compatible with a synchronous dynamic random access memory (SDRAM).
21. A method of operating a memory device comprising: monitoring a supply voltage of the memory device; setting a latch circuit to a default data state if the supply voltage is below a predetermined voltage; and setting the latch circuit to a second data state if the supply voltage is above the predetermined voltage.
22. The method of claim 21 further comprises reading the latch circuit using a controller located external to the memory device.
23. The method of claim 21 further comprises performing an initialization operation after the latch circuit is set to the second data state.
24. A method of operating a non-volatile memory comprising: detecting an operating error; and performing a status check to determine if a power supply voltage of the non-volatile memory dropped below a threshold voltage level, wherein performing the status check includes reading a brown-out latch circuit.
25. The method of claim 24 further comprises performing a reset operation on the non-volatile memory if the power supply voltage of the non-volatile memory dropped below the threshold voltage level.
26. The method of claim 25 wherein reset operation comprises loading volatile register with operating parameter data and placing the brown-out latch in a default state.
27. A synchronous flash memory device comprising: an array of non-volatile memory cells; a voltage detection circuit to monitor the supply voltage and provide a signal when the supply voltage drops below a predetermined value; a latch coupled to the voltage detection circuit, wherein the latch is programmed to indicate when the supply voltage dropped below the predetermined value; and a package having a plurality of interconnects arranged in a pattern compatible with a synchronous dynamic random access memory (SDRAM).
28. The synchronous flash memory device further comprising: a write enable connection (WE ) to receive a write enable signal; a column address strobe connection (CAS ) to receive a column address strobe signal; a row address strobe connection (RAS ) to receive a row address strobe signal; and a chip select connection (CS ) to receive a chip select signal.
29. A system comprising: a power supply to provide a supply voltage; a memory controller; and a flash memory device coupled to the memory controller and the power supply, the flash memory device comprises, a power supply input connection, a voltage comparator to compare a voltage provided on the power supply input connection to a reference voltage, and a programmable storage circuit to indicate if the voltage on the power supply input is greater than or less than the reference voltage.
30. A system comprising: a power supply to provide a supply voltage; a memory controller; and a memory device coupled to the memory controller and the power supply, the memory device comprises, a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value, and a brown-out latch circuit programmable to a first data state after an initialization operation is performed, the brown-out latch is programmable to a second state in response to the voltage detection circuit if the supply voltage drops below the predetermined value.
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May 22, 2001
April 2, 2002
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