A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test, which comprises the steps of: inducing a high potential on some of the word lines resulting in active word lines; floating remaining ones of the word lines not induced by the high potential at a negative word line potential with a high impedance, the remaining ones of the word lines defining inactive word lines; ramping down the active word lines to a low potential; and subsequently reconnecting all of the word lines to the negative word line potential.
2. The method according to claim 1 , which comprises connecting the inactive word lines to the negative word line potential before the active word lines are ramped down.
3. The method according to claim 1 , which comprises setting the negative word line potential to approximately 0.3 V.
4. The method according to claim 1 , which comprises applying the negative word line potential to the word lines through a transistor.
5. The method according to claim 1 , which comprises setting the high potential to be a voltage level of approximately 2.9 volts.
6. The method according to claim 1 , which comprises setting the low potential to be approximately 0 volts.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 29, 2001
April 9, 2002
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.