A novel fuse structure for a semiconductor integrated circuit device and the method of manufacturing the semiconductor integrated circuit device is disclosed. The fuse structure is comprised of a first interconnection metal layer formed on a semiconductor substrate; an inter-metal dielectric layer formed on the first interconnection metal layer having a via exposing the first interconnection metal layer; a via plug filling up the via; a metal layer for a fuse and a second interconnection metal layer consecutively deposited on the via plug and the inter-metal dielectric layer; and an opening area exposing the metal layer for a fuse is positioned more than twice the thickness of the second interconnection metal layer from the via. With the present invention, a contact failure which can result from a damage to via plug in a subsequent stripping step can be prevented. Also, a passivation layer formed after opening the fuse area prevents a short-circuit between adjacent fuses in a subsequent laser repairing process.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a fuse structure for a semiconductor integrated circuit device in which multiple interconnection metal layers are connected through a via comprises steps of: sequentially forming a metal barrier layer for a fuse and an interconnection metal layer on said via; forming a first passivation layer on said interconnection metal layer; patterning said first passivation layer to define a fuse opening area that is positioned more than twice the thickness of said interconnection metal layer from said via; and forming a fuse area by exposing said metal barrier layer for a fuse by wet etching said interconnection metal layer using said first passivation layer as a mask.
2. A method for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein said metal barrier layer for a fuse is composed of titanium (Ti) and titanium nitride (TiN).
3. A method for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein a wet etching of said interconnection metal barrier layer is performed using a chemical etchant having a selectivity between said metal barrier layer and said interconnection metal layer.
4. A method for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the thickness of said first passivation layer is greater than 3000 .
5. A method for manufacturing a semiconductor integrated circuit device according to claim 1 , after forming said fuse area, further comprising forming a second passivation layer.
6. A method for manufacturing a semiconductor integrated circuit device according to claim 1 , after the step of forming said first passivation layer, further comprising forming a second passivation layer on said first passivation layer.
7. A method for manufacturing a semiconductor integrated circuit device according to claim 5 , said second passivation layer is composed of a nitride.
8. A method for manufacturing a semiconductor integrated circuit device according to claim 6 , said second passivation layer is composed of a nitride.
9. A method for manufacturing a semiconductor integrated circuit device according to claim 5 , the thickness of said second passivation layer is less than 8000 .
10. A method for manufacturing a semiconductor integrated circuit device according to claim 6 , the thickness of said second passivation layer is less than 8000 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 21, 1999
April 16, 2002
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