A memory device includes a memory array and a configurable decoder circuit operatively associated with the memory array and configurable to one of a first state or a second state. In the first state, the configurable decoder circuit is operative, responsive to receipt of an address associated with a portion, e.g., a block, of the memory array, to select the portion while producing a first status signal. In the second state, the configurable decoder circuit is operative, responsive to receipt of an address associated with the portion of the memory array, to prevent selection of the portion while producing a second status signal. The first status signal may indicate, for example, that the portion is valid, while the second status signal may indicate that the portion is invalid. The configurable decoder circuit may include a plurality of configurable block decoder circuits, a respective one of which is coupled to a respective one of a plurality of memory blocks and configurable to one of a first state or a second state. In the first state, the configurable block decoder circuit is operative, responsive to receipt of an address associated with the corresponding memory block, to select the corresponding memory block while producing a first status signal. In the second state, the configurable block decoder circuit is operative, responsive to receipt of an address associated with the corresponding memory block, to prevent selection of the corresponding memory block while producing a second status signal. Related memory device operating methods are also discussed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: a memory array including a plurality of memory blocks; and a plurality of configurable block decoder circuits, respective ones of which are operatively associated with respective memory blocks of said plurality of memory blocks, wherein said configurable block decoder circuits are individually configurable to one of a first state or a second state, wherein each of said configurable block decoder circuits in the first state is operative, responsive to receipt of a block address associated with the associated memory block, to select the associated memory block while producing a first status signal, and wherein each of said configurable block decoder circuits in the second state is operative, responsive to receipt of the block address associated with the associated memory block, to prevent selection of the associated memory block without selection of an alternative memory block while producing a second status signal.
2. A memory device according to claim 1 , wherein the first status signal indicates that the corresponding memory block is valid, and wherein the second status signal indicates that the corresponding memory block is invalid.
3. A memory device according to claim 1 , wherein at least one of said configurable block decoder circuits is fuse-programmable.
4. A memory device according to claim 1 , wherein at least one of the configurable block decoder circuits comprises: a block address decoder circuit that receives block addresses and that generates an address decoder output signal, said block address decoder output signal taking on a first state in response to a select block address and taking on a second state in response to a block address other than said select block address; and a programmable status signal generating circuit responsive to said block address decoder circuit and including a programmable element, wherein said programmable status signal generating circuit is operative to produce a status signal in response to the block address decoder output signal, said status signal having one of a first state or a second state depending on a state of said programmable element.
5. A memory device according to claim 4 , wherein said programmable element comprises a fuse.
6. A memory device according to claim 4 : wherein said at least one of the configurable block decoder circuits further comprises a memory block control signal generating circuit responsive to said block address decoder circuit and to said status signal generating circuit and operative to produce a memory block control signal therefrom, said memory block control signal taking on a first state when said block address decoder output signal is in said first state and said status signal is in said first state and taking on a second state when said block address decoder output signal is in said first state and said status signal is in said second state; and wherein said corresponding memory block is responsive to said memory block control signal.
7. A memory device according to claim 4 , further comprising a status output circuit responsive to said block address decoder output signal and to said status signal, said status output circuit producing a status output signal taking on a first state when said block address decoder output signal is in said first state and said status signal is in said first state and taking on a second state when said block address decoder output signal is in said first state and said status signal is in said second state.
8. A memory device according to claim 4 : wherein the block address decoder circuit comprises a multi-input NAND gate circuit that generates the block address decoder output signal; and wherein the programmable status signal generating circuit comprises: a first inverter that receives the block address decoder output signal and generates an inverted block decoder output signal therefrom; an NMOS transistor having a gate electrode that receives the inverted block decoder output signal and a source electrode coupled to a signal ground node; a fuse connected between a drain electrode of the NMOS transistor and a power supply node; and a second inverter having an input coupled to the drain electrode of the NMOS transistor and that produces the status signal from a signal at the drain electrode of the NMOS transistor.
9. A memory device according to claim 8 , further comprising: a discharge circuit comprising series connected second and third NMOS transistors, wherein the second NMOS transistors has gate electrode that receives the status signal and a source electrode coupled to a drain electrode of the third NMOS transistor, and wherein the third NMOS transistor has a gate electrode that receives the inverted block address decoder output signal and a source electrode coupled to the signal ground; and a status output circuit comprising a buffer circuit with a depletion-mode transistor coupled to an input thereof, the depletion-mode transistor having a drain electrode coupled to the power supply node and gate and source electrodes coupled to a drain electrode of the second NMOS transistor.
10. An integrated circuit memory device, comprising: a memory array including a plurality of memory blocks; and a configurable block decoder circuit configurable to generate a status signal in response to receipt of an address for one of said plurality of memory blocks of said memory array in lieu of selecting any of said plurality of memory blocks, wherein said configurable block decoder circuit is configurable to one of: a first state in which said configurable block decoder circuit is operative, responsive to receipt of the address associated with the one memory block of the plurality of memory blocks, to select said one memory block while generating a first status signal; and a second state in which said configurable block decoder circuit is operative, responsive to receipt of the address signal associated with said one memory block, to prevent selection of said one memory block while generating a second status signal.
11. A memory device according to claim 10 , wherein said configurable block decoder circuit is fuse-programmable.
12. A memory device according to claim 10 , wherein the second status signal indicates that said one of said plurality of memory blocks of said memory array is invalid.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 28, 1999
April 16, 2002
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