A physical layer device (PHY) device in an Ethernet LAN is configured to permit ease of testing of its transmitter logic. The PHY device comprises a reset extension circuit for latching on the clock signals from a phase-locked loop (PLL) after the PLL has stabilized upon power-up or reset. The PHY device transmits a known valid bit pattern for testing purposes. A signal analyzer receives the transmitted bit pattern from the PHY device and compares the received bit pattern with a known valid bit pattern. A match indicates the proper operation of the PHY device transmitter logic.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system for testing a networking device comprising: a phase-locked loop (PLL) for generating a transmit clock signal in response to a basic clock signal; a reset extension circuit for latching the basic clock signal and the transmit clock signal when the PLL stabilizes, and for generating a secondary reset signal; a physical layer (PHY) device generating encoded signals that represent a known valid bit pattern, wherein an initial polarity state of the encoded signals is based upon the secondary reset signal; and a signal analyzer circuit for checking whether a transmitted bit pattern associated with the generated encoded signals matches the known valid bit pattern by decoding the encoded signals and comparing the transmitted bit pattern with the known valid bit pattern, a match between the transmitted bit pattern and the known valid bit pattern indicating operation of the PHY device in accordance with a prescribed operation.
2. The system as in claim 1 , wherein the reset extension circuit comprises: a counter for incrementing to a stop value that corresponds to a period required for the PLL to stabilize; a first flip-flop for latching the basic clock signal and providing an output signal in response to a reset deassert signal and upon the counter reaching the stop value; and a second flip-flop coupled to the first flip-flop for latching the transmit clock signal and outputting the secondary reset signal in response to the reset deassert signal and upon the counter being incremented to the stop value.
3. The system as in claim 1 , further comprising a PECL (Pseudo-Emitter Coupled Logic) circuit for generating an NRZI signal with the initial polarity state, the PECL circuit comprising: an XOR gate for receiving an NRZ signal at a first input; an OR gate for receiving an output signal of the XOR gate and the secondary reset signal; and a flip-flop for outputting the NRZI signal in response to an output signal of the OR gate and the basic clock signal, the NRZI signal being fed back to a second input of the XOR gate.
4. The system as in claim 1 , wherein the PHY device comprises a multi-level transmission-3 (MLT-3) circuit for generating a MLT-3 signal with the initial polarity state, the MLT-3 circuit comprising: a first XOR gate for receiving a NRZ signal at a first input; a first OR gate for receiving the secondary reset signal and an output signal from the first XOR gate; a first flip-flop for generating a first MLT-3 signal in response to an output signal of the first OR gate and the transmit clock signal, the first MLT-3 signal being fed back to a second input of the first XOR gate; an inverter for receiving the output of the first OR gate; an AND gate for receiving the output of the inverter and the first MLT-3; a second XOR gate for receiving the output of the AND gate; a second OR gate for receiving the output of the second XOR gate and the secondary reset signal; and a second flip-flop for generating a second MLT-3 signal in response to an output signal of the second OR gate and the transmit clock signal, the second MLT-3 signal being fed back to a second input of the second XOR gate.
5. The system as in claim 1 , wherein the basic clock signal has a frequency of 25 MHz and the transmit clock signal has a frequency of 125 MHz.
6. The system as in claim 1 , wherein the encoded signals conform to an IEEE 802.3 protocol.
7. A system for testing a networking device comprising: a physical layer (PHY) device generating encoded signals that represent a known valid bit pattern, the PHY device comprising, a phase-locked loop (PLL) for generating a transmit clock signal in response to a basic clock signal; a reset extension circuit for latching the basic clock signal and the transmit clock signal when the PLL stabilizes, and for generating a secondary reset signal, wherein an initial polarity state of the encoded signals is based upon the secondary reset signal; and a signal analyzer circuit for checking whether a transmitted bit pattern associated with the generated encoded signals matches the known valid bit pattern by decoding the encoded signals and comparing the transmitted bit pattern with the known valid bit pattern, a match between the transmitted bit pattern and the known valid bit pattern indicating operation of the PHY device in accordance with a prescribed operation.
8. The system as in claim 7 , wherein the reset extension circuit comprises: a counter for counting clock cycles and incrementing to a stop value that corresponds to a period for the PLL to stabilize; a first flip-flop for latching the basic clock signal in response to a reset deassert signal and upon the counter being incremented to the stop value; and a second flip-flop coupled to the first flip-flop for latching the transmit clock signal and outputting the secondary reset signal in response to the reset deassert signal and upon the counter reaching the stop value.
9. The system as in claim 7 , further comprising a PECL circuit for generating a NRZI signal with the initial polarity state, the PECL circuit comprising: an XOR gate for receiving a NRZ signal at a first input lead; an OR gate for receiving an output signal of the XOR gate and the secondary reset signal; and a flip-flop for outputting the NRZI signal in response to an output signal of the OR gate and the basic clock signal, the NRZI signal being fed back to a second input lead of the XOR gate.
10. The system as in claim 7 , wherein the PHY device comprises a multi-level transmission-3 (MLT-3) circuit for generating a MLT-3 signal with the initial polarity state, the MLT-3 circuit comprising: a first XOR gate for receiving a NRZ signal at a first input; a first OR gate for receiving the secondary reset signal and an output signal from the first XOR gate; a first flip-flop for generating a first MLT-3 signal in response to an output signal of the first OR gate and the transmit clock signal, the first MLT-3 signal being fed back to a second input of the first XOR gate; an inverter for receiving the output of the first OR gate; an AND gate for receiving the output of the inverter and the first MLT-3; a second XOR gate for receiving the output of the AND gate; a second OR gate for receiving the output of the second XOR gate and the secondary reset signal; and a second flip-flop for generating a second MLT-3 signal in response to an output signal of the second OR gate and the transmit clock signal, the second MLT-3 signal being fed back to a second input of the second XOR gate.
11. The system as in claim 7 , wherein the basic clock signal has a frequency of 25 MHz and the transmit clock signal has a frequency of 125 MHz.
12. The system as in claim 7 , wherein the encoded signals conform to an IEEE 802.3 protocol.
13. A method for deterministically testing transmitter logic of a physical layer (PHY) device, the method comprising: generating a transmit clock signal by a phase-locked loop (PLL) in response to a basic clock signal; latching the basic clock signal and the transmit clock signal when the PLL stabilizes; supplying a secondary reset signal in response to the transmit clock signal; generating encoded signals based upon a known valid bit pattern, the encoded signals exhibiting an initial polarity state that is determined based upon the secondary reset signal; decoding the encoded signals to yield a transmitted bit pattern; and comparing the transmitted bit pattern with the known valid bit pattern, a match between the transmitted bit pattern and the known valid bit pattern indicating operation of the transmitter logic in accordance with a prescribed operation.
14. The method as in claim 13 , wherein the step of computing comprises incrementing a counter to a stop value that corresponds to a period for the PLL to stabilize, and the step of latching is further based upon the stop value and a reset deassert signal.
15. The method as in claim 13 , further comprising generating the encoded signals according to NRZI protocol from an NRZ signal in response to the secondary reset signal and the basic clock signal.
16. The method as in claim 13 , further comprising generating the encoded signals according to MLT-3 protocol from an NRZ signal in response to the secondary reset signal and the transmit clock signal.
17. The method as in claim 13 , wherein the encoded signals conform to an IEEE 802.3 protocol.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 29, 1999
May 7, 2002
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