A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from extending into the voids during the etching of the via openings. Accordingly, metal deposition of the voids during metal deposition of the vias is avoided. As a result, the semiconductors so formed has reduced capacitance between the interconnects and improved reliability since the voids are cleared of any metal deposition.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device, comprising the steps of: providing a substrate with a first dielectric layer formed thereon; depositing a first conductive layer over said first dielectric layer; patterning and etching said first conductive layer to form a first interconnect, a second interconnect and a gap between said first interconnect and said second interconnect, wherein said gap is defined by walls of said first interconnect and said second interconnect; depositing a second dielectric layer over said first interconnect and said second interconnect by high density plasma deposition, said depositing said second dielectric layer including depositing along said walls, said second dielectric layer formed to a thickness sufficient to fill said gap with a void formed therein, wherein said second dielectric layer includes a first crest portion over said first interconnect, a second crest portion over said second interconnect and a recess portion over said gap; depositing an etch stop layer over said second dielectric layer, said depositing said etch stop layer including depositing over said first crest portion, said second crest portion and said recess portion; and planarizing said etch stop layer and said second dielectric layer to obtain a substantially planar surface, wherein said planar surface includes a portion of said second dielectric layer over said first interconnect and said second interconnect, and an etch stop recess portion formed of said etch stop layer over said recess portion whereby said void remains in said second dielectric layer.
2. The method as claimed in claim 1 wherein said substrate is a semiconductor substrate.
3. The method as claimed in claim 1 wherein said first conductor layer comprises a material selected from the group consisting of aluminum, tungsten, polysilicon, copper, a compound thereof, an alloy thereof, and a combination thereof.
4. The method as claimed in claim 1 wherein said second dielectric layer comprises a material selected from the group consisting of undoped silicate glass (USG), phospho silicate glass (PSG), fluorinated silicate glass (FSG), and borophospho silicate glass (BPSG).
5. The method as claimed in claim 1 wherein the step of depositing said second dielectric layer over said first interconnect and said second interconnect by high density plasma deposition is performed using high density plasma chemical vapor deposition.
6. The method as claimed in claim 1 wherein said etch stop layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon carbide.
7. The method as claimed in claim 1 wherein the step of planarizing said etch stop layer and said second dielectric layer is performed using chemical-mechanical polishing.
8. The method as claimed in claim 1 including the steps of: depositing a third dielectric layer over said planar surface; patterning and etching said third and second dielectric layers to form a first opening and a second opening over said first interconnect and second interconnect respectively, said first opening exposes a portion of said first interconnect and said second opening exposes a portion of said second interconnect, wherein said etch stop recess portion has sufficiently high etch selectivity with respect to said second dielectric layer to minimize etching through said etch stop recess portion; and depositing a second conductive layer over said third dielectric layer, said second conductive layer formed to a thickness sufficient to fill said first opening and said second opening.
9. The method as claimed in claim 8 wherein said third dielectric layer comprises a material selected from the group consisting of undoped silicate glass (USG), phospho silicate glass (PSG), fluorinated silicate glass (FSG), and borophospho silicate glass (BPSG).
10. The method as claimed in claim 8 wherein said second conductor layer comprises a material selected from the group consisting of aluminum, tungsten, polysilicon, copper, a compound thereof, an alloy thereof, and a combination thereof.
11. A method of manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate with a first dielectric layer formed thereon; depositing a first conductive layer over said first dielectric layer; patterning and etching said first conductive layer to form a first interconnect, a second interconnect and a gap between said first interconnect and said second interconnect, wherein said gap is defined by walls of said first interconnect and said second interconnect; depositing a second dielectric layer over said first interconnect and said second interconnect by high density plasma deposition, said depositing said second dielectric layer including depositing along said walls, said second dielectric layer formed to a thickness sufficient to fill said gap with a void formed therein, wherein said second dielectric layer includes a first crest portion over said first interconnect, a second crest portion over said second interconnect and a recess portion over said gap; depositing an etch stop layer over said second dielectric layer, said depositing said etch stop layer including depositing over said first crest portion, said second crest portion and said recess portion; planarizing said etch stop layer and said second dielectric layer to obtain a substantially planar surface by chemical-mechanical polishing, wherein said planar surface includes a portion of said second dielectric layer over said first interconnect and said second interconnect, and an etch stop recess portion formed of said etch stop layer over said recess portion whereby said void remains in said second dielectric layer; depositing a third dielectric layer over said planar surface; patterning and etching said third and second dielectric layers to form a first opening and a second opening over said first interconnect and second interconnect respectively, said first opening exposes a portion of said first interconnect and said second opening exposes a portion of said second interconnect, wherein said etch stop recess portion has sufficiently high etch selectivity with respect to said second dielectric layer to minimize etching through said etch stop recess portion; and depositing a second conductive layer over said third dielectric layer, said second conductive layer formed to a thickness sufficient to fill said first opening and said second opening.
12. The method as claimed in claim 11 wherein said first conductor layer comprises a material selected from the group consisting of aluminum, tungsten, polysilicon, copper, a compound thereof, an alloy thereof, and a combination thereof.
13. The method as claimed in claim 11 wherein said second dielectric layer comprises a material selected from the group consisting of undoped silicate glass (USG), phospho silicate glass (PSG), fluorinated silicate glass (FSG), and borophospho silicate glass (BPSG).
14. The method as claimed in claim 11 wherein the step of depositing said second dielectric layer over said first interconnect and said second interconnect by high density plasma deposition is performed using high density plasma chemical vapor deposition.
15. The method as claimed in claim 11 wherein said etch stop layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon carbide.
16. The method as claimed in claim 11 wherein said third dielectric layer comprises a material selected from the group consisting of undoped silicate glass (USG), phospho silicate glass (PSG), fluorinated silicate glass (FSG), and borophospho silicate glass (BPSG).
17. The method as claimed in claim 11 wherein said second conductor layer comprises a material selected from the group consisting of aluminum, tungsten, polysilicon, cop, a compound thereof, an alloy thereof, and a combination thereof.
18. A method of manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate with a first dielectric layer formed thereon; depositing a first conductive layer over said first dielectric layer, wherein said first conductor layer comprises a material selected from the group consisting of aluminum, tungsten, polysilicon, copper, a compound thereof, an alloy thereof, and a combination thereof; patterning and etching said first conductive layer to form a first interconnect, a second interconnect and a gap between said first interconnect and said second interconnect, wherein said gap is defined by walls of said first interconnect and said second interconnect; depositing a second dielectric layer over said first interconnect and said second interconnect by high density plasma chemical vapor deposition, said depositing said second dielectric layer including depositing along said walls, said second dielectric layer formed to a thickness sufficient to fill said gap with a void formed therein, wherein said second dielectric layer includes a first crest portion over said first interconnect, a second crest portion over said second interconnect and a recess portion over said gap; depositing an etch stop layer over said second dielectric layer, said depositing said etch stop layer including depositing over said first crest portion, said second crest portion and said recess portion; planarizing said etch stop layer and said second dielectric layer to obtain a substantially planar surface by chemical-mechanical polishing, wherein said planar surface includes a portion of said second dielectric layer over said first interconnect and said second interconnect, and an etch stop recess portion formed of said etch stop layer over said recess portion; depositing a third dielectric layer over said planar surface, wherein said third dielectric layer comprise a material selected from the group consisting of undoped silicate glass (USG), phospho silicate glass (PSG), fluorinated silicate glass (FSG), and borophospho silicate glass (BPSG); patterning and etching said third dielectric layers to form a first opening and a second opening over said first interconnect and second interconnect respectively, said first opening exposes a portion of said first interconnect and said second opening exposes a portion of said second interconnect, wherein said etch stop recess portion has sufficiently high etch selectivity with respect to said second dielectric to minimize etching through said etch stop recess portion; and depositing a second conductive layer over said third dielectric layer, said second conductive layer formed to a thickness sufficient to fill said first opening and said second opening, wherein said second conductor layer comprises a material selected from the group consisting of aluminum, tungsten, polysilicon, copper, a compound thereof, an alloy thereof, and a combination thereof.
19. The method as claimed in claim 18 wherein said second dielectric layer comprises a material selected from the group consisting of undoped silicate glass (USG), phospho silicate glass (PSG), fluorinated silicate glass (FSG), and borophospho silicate glass (BPSG).
20. The method as claimed in claim 18 wherein said etch stop layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon carbide.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 20, 1999
May 14, 2002
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