Semiconductor memory device capable of performing stable sensing operation even under low power supply voltage environment

1. A semiconductor memory device comprising: a pair of bit lines; a memory cell connected to either one of said pair of bit lines and storing data; a sense amplifier for sensing and amplifying a potential difference of said pair of bit lines, the potential difference being caused in accordance with the data read from said memory cell; a first power feed line for supplying a driving power to said sense amplifier; a second power feed line for supplying the driving power to said sense amplifier; a first sense amplifier driving transistor connected between said first power feed line and said sense amplifier; a second sense amplifier driving transistor connected between said second power feed line and said sense amplifier; a first decoupling capacitor connected between said first power feed line and a power source providing a power source potential different in logic level from the driving power; a second decoupling capacitor connected between said second power feed line and said power source; a first power feed circuit for precharging said first power feed line and said first decoupling capacitor to a first potential prior to activation of said sense amplifier; and a second power feed circuit for charging said second power feed line and said second decoupling capacitor to a second potential different in level from said first potential.

2. The semiconductor memory device according to claim 1 , wherein said driving power is for driving one of said pair of bit lines to a potential higher than potential of the other bit line of said pair of bit lines when the data stored in said memory cell is read out, and said second potential is lower than said first potential.

3. The semiconductor memory device according to claim 1 , wherein said first power feed circuit charges said first power feed line and said first decoupling capacitor in response to a precharge signal activated when said sense amplifier is in a standby state.

4. The semiconductor memory device according to claim 1 , wherein said first sense amplifier driving transistor and said second sense amplifier driving transistor are activated at timings different from each other.

5. The semiconductor memory device according to claim 1 , wherein said first sense amplifier driving transistor receives, at a gate thereof, a first sense amplifier activating signal, and said second sense amplifier driving transistor receives, at a gate thereof, a second sense amplifier activating signal activated later than said first sense amplifier activating signal is activated.

6. The semiconductor memory device according to claim 1 , wherein said first potential is an external power potential applied externally, and said second power feed circuit comprises a voltage down converting circuit for down converting said external power potential for supply onto said second power feed line.

7. The semiconductor memory device according to claim 1 , wherein said first decoupling capacitor is disposed between a region where said sense amplifier is disposed and a region where said memory cell is disposed.

8. The semiconductor memory device according to claim 1 , wherein said memory cell and said sense amplifier are disposed in a memory array region, and said second decoupling capacitor is disposed in a peripheral circuit portion outside said memory array region.

9. A semiconductor memory device comprising: a pair of bit lines; a memory cell connected to either one of said pair of bit lines and storing data; a sense amplifier for sensing and amplifying a potential difference between said pair of bit lines, the potential difference being caused in accordance with the data read from said memory cell; a power feed line for feeding a driving power to said sense amplifier; a sense amplifier driving transistor connected between said power feed line and said sense amplifier; a variable decoupling capacitor connected to said power feed line and having a decoupling capacitance value changed in response to a control signal; a constant decoupling capacitor connected to said power feed line and having a predetermined capacitance; a charger circuit for charging said power feed line, said constant decoupling capacitor, and said variable decoupling capacitor from a predetermined power source; and a monitoring and controlling circuit for monitoring a potential of said predetermined power source, and generating said control signal according to the result of monitoring to control the capacitance value of said variable decoupling capacitor.

10. The semiconductor memory device according to claim 9 , wherein said driving power is for driving one of said pair of bit lines to a potential higher than a potential of the other bit line of said pair of bit lines, in accordance with the data read from said memory cell.

11. The semiconductor memory device according to claim 9 , wherein said monitoring and control circuit comprises: a voltage dividing circuit receiving and dividing a potential of said predetermined power source for supplying a divided potential; reference potential generation circuitry for generating at least one reference potential at a predetermined potential level; and a capacitor control circuit receiving said divided potential and said reference potential, for comparing said divided potential and said reference potential, and generating and outputting said control signal to control the capacitance value of said variable decoupling capacitor in accordance with the result of comparison.

12. The semiconductor memory device according to claim 11 , wherein said reference potential generator circuitry outputs a plurality of reference potentials different in level from each other as said at least one reference potential; and said variable decoupling capacitor comprises discrete capacitor sections not greater in number than said plurality of reference potentials at different levels.

13. The semiconductor memory device according to claim 12 , wherein each of said plurality of discrete capacitor sections comprises: a p-channel transistor and an n-channel transistor connected in series between said power feed line and a power source different from said predetermined power source and receiving a common control signal as said control signal on their respective gates; and a capacitor connected between said power feed line and a connection node between said p-channel transistor and said n-channel transistor.

14. The semiconductor memory device according to claim 11 , wherein said reference potential generation circuitry generates a plurality of reference potentials different in potential level from each other as said at least one reference potential, said capacitor control circuit generates a plurality of capacitor controlling signals as said control signal according to the result of comparison between each of said plurality of reference potentials and the potential of said predetermined power source, and said variable decoupling capacitor comprises a plurality of discrete capacitor sections, disposed corresponding to said plurality of capacitor controlling signals, each having a decoupling capacitance value set in accordance with a corresponding capacitor controlling signal.

15. The semiconductor memory device according to claim 14 , wherein said capacitor control circuit comprises: a transfer circuit rendered conductive for a predetermined period for taking in the divided potential obtained through division of the potential of said predetermined power source; comparison circuits, provided corresponding to said plurality of reference potentials, each for performing a comparison between said divided potential taken in through said transfer circuit and a corresponding reference potential; and control signal retaining circuitry for retaining results of the comparison and outputting the controlling signals for controlling activation of corresponding discrete capacitor sections as said capacitor controlling signals in accordance with said results of the comparison, each of said discrete capacitor sections serving as a decoupling capacitor for said power feed line when activated.

16. The semiconductor memory device according to claim 9 , wherein said charger circuit comprises a charging transistor connected between said predetermined power source and said power feed line and stopping charging in accordance with inactivation of a precharge signal, said prechage signal being activated when said sense amplifier is in a standby state.

17. The semiconductor memory device according to claim 16 , wherein said predetermined power source is an external power supply receiving an externally applied power supply potential.

18. The semiconductor memory device according to claim 16 , further comprising a voltage down converting circuit for down converting the potential of said predetermined power source to feed a resultant down converted potential to said power feed line.

19. The semiconductor memory device according to claim 9 , further comprising a fixed decoupling capacitor connected to said power feed line and having a fixed capacitance value.