An almost full flag is asserted when all but one of the rows of a CAM array contain valid data, as indicated by corresponding valid bits. In one embodiment, the almost full flag is generating using match logic and multiple match logic, where the match logic asserts a first signal when at least one of the CAM rows contains invalid data, and the multiple match logic asserts a second signal when more than one CAM row contains invalid data. The almost full flag is asserted when the first asserting is asserted indicating there is at least one available row and the second signal is de-asserted indicating there is no more than one available row. Thus, when asserted, the almost full flag indicates that there is only one available CAM row. Subsequent instructions are monitored to detect an instruction which calls for writing valid data to the one available CAM row. The full flag is asserted when such an instruction is detected while the almost full flag is asserted.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for generating a full flag indicating that an associated content addressable memory (CAM) array is full, the CAM array having associated therewith a plurality of valid bits each indicative of whether a corresponding row of the CAM array contains valid data, the method comprising: asserting an almost full flag when the valid bits indicate that all but one of the corresponding rows of the CAM array contain valid data; and asserting the full flag when a subsequent instruction results in the valid bits indicating that all of the corresponding rows of the CAM array contain valid data.
2. The method of claim 1 , wherein the full flag is asserted in response to the subsequent instruction which causes valid data to be written to the but one row of the CAM array which does not contain valid data.
3. The method of claim 1 , wherein asserting the almost full flag further comprises: asserting a first signal when the valid bits indicate that at least one of the rows of the CAM array contains invalid data; de-asserting a second signal when the valid bits indicate that not more than one of the rows of the CAM array contain invalid data; and logically combining the first and second signals.
4. The method of claim 3 , wherein the first signal is generated by a match circuit and the second signal is generated by a multiple match circuit.
5. The method of claim 1 , wherein asserting the full flag further comprises determining whether the subsequent instruction calls for writing data to a next free address of the CAM array.
6. The method of claim 1 , wherein asserting the full flag further comprises: detecting whether the subsequent instruction calls for writing data to a specified address; comparing the specified address to a next free address of the CAM array; and asserting the full flag if the specified address matches the next free address.
7. A full flag logic structure for generating a full flag when an instruction calls for writing valid data to the last available row of an associated content addressable memory (CAM) array, the structure comprising: an almost full flag logic circuit having an input coupled to receive valid bits from the CAM array and having an output terminal, the valid bits indicative of whether a corresponding row of the CAM array contains valid data; and a full flag logic circuit having a first input terminal coupled to the output terminal of the almost full flag logic circuit, a second input terminal coupled to receive an instruction bit from an associated instruction decoder, and an output terminal to provide the full flag.
8. The structure of claim 7 , wherein the full flag logic circuit further comprises a third input terminal coupled to receive a next free address of the array.
9. The structure of claim 7 , wherein the full flag logic circuit is coupled to receive an address specified for the instruction.
10. The structure of claim 7 , wherein the almost full flag circuit further comprises: a match logic circuit having an input coupled to receive the valid bits and having an output terminal; a multiple match circuit having an input coupled to receive the valid bits and having an output terminal; and a logic circuit having first and second input terminals coupled to the respective output terminals of the match logic circuit and the multiple match logic circuit, and having an output terminal to provide an almost full flag.
11. The structure of claim 10 , wherein the match logic circuit asserts a first signal when the valid bits indicate that at least one of the rows of the CAM array contains invalid data.
12. The structure of claim 11 , wherein the multiple match logic circuit de-asserts a second signal when the valid bits indicate that not more than one of the rows of the CAM array contain invalid data.
13. The structure of claim 10 , wherein the match logic circuit and the multiple match logic circuit are included within a priority encoder associated with the CAM array.
14. The structure of claim 8 , wherein the full flag logic circuit further comprises: a comparator having a first input coupled to receive the next free address, a second input for receiving an address specified for the instruction, and an output terminal; a first logic circuit having a first input terminal coupled to receive a first of the instruction bits, a second input terminal coupled to the output terminal of the comparator, and a output terminal; a second logic circuit having a first input terminal coupled to receive a second of the instruction bits, a second input terminal coupled to the output terminal of the first logic circuit, and an output terminal; and a third logic circuit having a first input terminal coupled to the output terminal of the almost full flag logic circuit, a second input terminal coupled to the output terminal of the second logic circuit, and an output terminal to provide the full flag.
15. The structure of claim 14 , wherein the first logic circuit comprises an AND gate, the second logic circuit comprises an OR gate, and the third logic circuit comprises an AND gate.
16. The structure of claim 14 , further comprising a fourth logic circuit coupled to the output terminal of the third logic circuit.
17. The structure of claim 16 , wherein the fourth logic circuit comprises: an exclusive-OR gate having a first input terminal coupled to the output terminal of the third logic circuit, a second input terminal, and an output terminal; and a latch having a data input terminal coupled to the first input terminal of the exclusive-OR gate, an enable terminal coupled to the output terminal of the exclusive OR gate, and an output terminal coupled to provide the full flag.
18. The structure of claim 7 , wherein the almost full flag logic circuit comprises a multiple match circuit having an input to receive the valid bits and having an output terminal coupled to the full flag circuit, the multiple match circuit to assert an almost full flag when the valid bits indicate that not more than one of the rows of the CAM array contains invalid data.
19. A full flag logic structure for generating a full flag when an associated content addressable memory (CAM) array is full, the CAM array having associated therewith a plurality of valid bits each indicative of whether a corresponding row of the CAM array contains valid data, the structure comprising: means for asserting an almost full flag when the valid bits indicate that all but one of the corresponding rows of the CAM array contain valid data; and means for asserting the full flag when an instruction provided to the CAM array calls for writing valid data to the last available row of the CAM array.
20. The structure of claim 19 , wherein the means for asserting the almost full flag further comprises: means for asserting a first signal when the valid bits indicate that at least one of the rows of the CAM array contains invalid data; means for de-asserting a second signal when the valid bits indicate that not more than one of the rows of the CAM array contains invalid data; and a logic circuit configured to combine the first and second signals to provide the almost full flag.
21. The structure of claim 19 , wherein the means for asserting the full flag further comprises: means for monitoring one or more instruction bits to determine if the instruction calls for writing valid data to the one row of the CAM array which does not contain valid data.
22. The structure of claim 21 , wherein the means for monitoring comprises means for determining whether the instruction calls for assertion of the valid bit of a next free address of the CAM array.
23. The structure of claim 21 , wherein the means for monitoring comprises: means for detecting whether the instruction calls for writing data to a specified address; means for comparing the specified address to a next free address of the CAM array; and means for asserting the full flag if the specified address matches the next free address.
24. A method for generating an almost full flag for a content addressable memory (CAM) array, the CAM array having associated therewith a plurality of valid bits each indicative of whether a corresponding row of the CAM array contains valid data, the method comprising: logically monitoring the valid bits; and determining that only one of the rows of the CAM array contains invalid data.
25. The method of claim 24 , wherein determining that only one of the rows of the CAM array contains invalid data further comprises: asserting a first signal when the valid bits indicate that at least one of the rows of the CAM array contains invalid data; de-asserting a second signal when the valid bits indicate that not more than one of the rows of the CAM array contain invalid data; and logically combining the first and second signals.
26. An almost full flag logic circuit for generating an almost full flag for a content addressable memory (CAM) array, the CAM array having associated therewith a plurality of valid bits each indicative of whether a corresponding row of the CAM array contains valid data, the circuit comprising: a match logic circuit having an input coupled to receive the valid bits and having an output terminal; a multiple match logic circuit having an input coupled to receive the valid bits and having an output terminal; and a logic circuit having first and second input terminals coupled to the respective output terminals of the match logic circuit and the multiple match logic circuit, and having an output terminal to provide the almost full flag.
27. The circuit of claim 26 , wherein the match logic circuit asserts a first signal when the valid bits indicate that at least one of the rows of the CAM array contains invalid data.
28. The circuit of claim 26 , wherein the multiple match logic circuit asserts a second signal when the valid bits indicate that more than one of the rows of the CAM array contain invalid data.
29. A content addressable memory (CAM) structure comprising: a CAM array having a plurality of rows of CAM cells and a plurality of valid bits corresponding to the rows of CAM cells; an instruction decoder coupled to the CAM array; almost full flag logic coupled to the CAM array to receive at least one of the valid bits, and having an output to provide an almost full flag signal; and full flag logic having a first input coupled to receive the almost full flag signal, a second input coupled to the instruction decoder, and having an output to provide a full flag signal.
30. The structure of claim 29 , wherein the almost full flag logic asserts the almost full flag signal when the valid bits indicate that not more than one of the rows of the CAM array contains invalid data.
31. The structure of claim 29 , wherein the full flag logic asserts the full flag signal when one or more instruction bits received from the instruction decoder indicate that valid data is to be written to the last available row of the CAM array.
32. The structure of claim 29 , wherein the almost full flag logic comprises: a match logic circuit having an input coupled to receive the valid bits and having an output terminal; a multiple match logic circuit having an input coupled to receive the valid bits and having an output terminal; and a logic circuit having first and second input terminals coupled to the respective output terminals of the match logic circuit and the multiple match logic circuit, and having an output terminal to provide the almost full flag signal.
33. The structure of claim 29 , wherein the almost full flag logic comprises a multiple match logic circuit having an input coupled to receive the valid bits and having an output terminal to provide the almost full flag signal.
34. The structure of claim 29 , wherein the almost full flag logic comprises: means for asserting the almost full flag signal when the valid bits indicate that all but one of the corresponding rows of the CAM array contain valid data.
35. The structure of claim 34 , wherein the means for asserting the almost full flag signal further comprises: means for asserting a first signal when the valid bits indicate that at least one of the rows of the CAM array contains invalid data; means for de-asserting a second signal when the valid bits indicate that not more than one of the rows of the CAM array contains invalid data; and a logic circuit configured to combine the first and second signals to provide the almost full flag signal.
36. The structure of claim 29 , wherein the full flag logic comprises: means for asserting the full flag signal when an instruction provided to the CAM array calls for writing valid data to the last available row of the CAM array.
37. The structure of claim 36 , wherein the means for asserting the full flag signal further comprises: means for monitoring one or more instruction bits to determine if the instruction calls for writing valid data to the one row of the CAM array which does not contain valid data.
38. The structure of claim 37 , wherein the means for monitoring comprises means for determining whether the instruction calls for assertion of the valid bit of a next free address of the CAM array.
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July 12, 1999
May 21, 2002
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