An inverse assembler and converter acquire binary code during inverse assembly of compiled programming code for a software application. A memory image file is generated during compiling of the programming code and a converter is used to trigger a physical address in a memory bus via a logic analyzer. A triggered logical address in the compiled programming code is determined. The triggered logical address is input into the converter. Trigger commands are provided to the logic analyzer that are used to trigger a physical address where binary code is stored in memory. The trigger commands are supplied to the logic analyzer and the memory bus is triggered. The physical address is acquired and converted into a logical address. The memory image file is searched for the logical address. The binary code is acquired from the memory image file at the logical address. The binary code corresponds to only machine code instructions performed during execution of the software application. The binary code is converted into machine code instructions so as to perform the inverse assembly of the compiled programming code for the software application.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for inverse assembly of a software application having a memory image file generated during compiling of programming code, said method comprising the steps of: determining a logical address indicating a location of a binary code; searching the memory image file for the logical address; acquiring the binary code at the logical address from the memory image file, the binary code corresponding to only machine code instructions performed during execution of the software application; and converting the acquired binary code into a first at least one machine code instruction so as to perform the inverse assembly of the compiled programming code for the software application.
2. The method, as claimed in claim 1 , wherein said step of determining a logical address further includes the steps of: probing only an address bus during execution of the software application; receiving a physical address corresponding to a location of the binary code in memory in response to the step of probing; and converting the received physical address into the logical address.
3. The method, as claimed in claim 1 , wherein the memory image file is selected from the group consisting of an S-record file, an elf file, a coff file, a plain binary file and an intel hex file.
4. A method for acquiring binary code during inverse assembly of compiled programming code for a software application using a converter to trigger a physical address in a memory bus via a logic analyzer, said method comprising the steps of: determining a triggered logical address in the compiled programming code; inputting the triggered logical address into the converter; providing a trigger command converting the triggered logical address into a physical address, wherein the physical address corresponding a location where binary code is stored in memory; supplying the trigger command to the logic analyzer; triggering the memory bus using the logic analyzer with the trigger command; acquiring the binary code from the memory bus; and converting the acquired binary code to at least one machine code instruction or a data value so as to perform inverse assembly on the software application.
5. The method, as claimed in claim 4 , wherein said step of determining the triggered logical address further includes the step of: pointing to a source code line of the software application, the source code corresponding to the triggered logical address.
6. The method, as claimed in claim 4 , wherein the trigger command comprises a plurality of trigger commands.
7. The method, as claimed in claim 4 , wherein said step of providing a trigger command further includes the step of: displaying the trigger command to a user.
8. The method, as claimed in claim 7 , wherein said step of supplying the trigger command further includes the step of; manually inputting the trigger command into the logic analyzer.
9. The method, as claimed in claim 4 , wherein the memory bus comprises an address bus, a data bus and a status bus.
10. A method for acquiring binary code during inverse assembly of compiled programming code for a software application having a memory image file generated during compiling of the programming code and that uses a converter to trigger a physical address in a memory bus via a logic analyzer, said method comprising the steps of: determining a triggered logical address in the compiled programming code; inputting the triggered logical address into the converter; providing a trigger command converting the triggered logical address into a physical address, wherein the physical address corresponds to binary code stored in memory; supplying the trigger command to the logic analyzer; triggering the memory bus using the logic analyzer with the trigger command; acquiring the physical address corresponding to binary code stored in memory; converting the acquired physical address into a logical address; searching the memory image file for the logical address; acquiring the binary code at the logical address from the memory image file, the binary code corresponding to only machine code instructions performed during execution of the software application; and converting the acquired binary code into a first at least one machine code instructions so as to perform the inverse assembly of the compiled programming code for the software application.
11. The method, as claimed in claim 10 , wherein the memory image file is selected from the group consisting of an S-record file, an elf file, a coff file, a plain binary file and an intel hex file.
12. The method, as claimed in claim 10 , wherein the logical command comprises a plurality of logical commands.
13. The method, as claimed in claim 10 , wherein said step of determining the triggered logical address further comprises the step of: pointing to a source code line of the software application, the source code corresponding to the triggered logical address.
14. The method, as claimed in claim 10 , wherein said step of providing a trigger command further includes the steps of: displaying trigger commands to a user.
15. The method, as claimed in claim 14 , wherein said step of supplying the trigger command further includes the steps of: manually inputting the trigger command into the logic analyzer.
16. The method, as claimed in claim 10 , wherein the memory bus comprises an address bus and a status bus.
17. An apparatus for acquiring binary code during inverse assembly of compiled programming code for a software application having a memory image file generated during compiling of the programming code, said apparatus having a converter and logic analyzer that triggers a physical address in a memory bus, said apparatus comprising: means for determining a triggered logical address in the compiled programming code; means for inputting the triggered logical address into the converter; means for providing a trigger command converting the triggered logical address into a physical address storing binary code in memory; means for supplying the trigger command to the logic analyzer; means for triggering the memory bus using the logic analyzer with the trigger commands; means for acquiring the physical address from the triggered memory bus corresponding to binary code stored in memory; means for converting the physical address into the logical address; means for searching the memory image file for the logical address; means for acquiring the binary code at the logical address from the memory image file, the binary code corresponding to only machine code instructions performed during execution of the software application; and means for converting the acquired binary code into a first at least one machine code instructions, whereby inversely assembling the compiled programming code for the software application.
18. The apparatus, as claimed in claim 17 , wherein the memory image file is selected from the group consisting of an S-record file, an elf file, a coff file, a plain binary file and an intel hex file.
19. The apparatus, as claimed in claim 17 , wherein the logical command comprises a plurality of logical commands.
20. The apparatus, as claimed in claim 17 , wherein the memory bus comprises an address bus and a status bus.
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June 25, 1999
May 21, 2002
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