An integrated memory has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and connected to a data line and amplifies data read from the normal memory cells. Furthermore, the memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected on the one hand to the line and on the other hand to the data line and, in the redundancy situation, serves for amplifying the data read from the normal memory cells. A method for repairing an integrated memory is also provided.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated memory, comprising: normal memory cells; a normal bit line connected to said normal memory cells for transferring data between said normal memory cells; a normal sense amplifier for amplifying data read from said normal memory cells; a line connecting said normal sense amplifier to said normal bit line; a data line connected to said normal sense amplifier; and a redundant sense amplifier for replacing said normal sense amplifier in a redundancy situation, said redundant sense amplifier connected to said line and to said data line and amplifying data read from said normal memory cells in the redundancy situation.
2. The integrated memory according to claim 1 , including: redundant memory cells; and a redundant bit line connecting said redundant memory cells for replacing said normal bit line connected to said line; one of said normal sense amplifier and said redundant sense amplifier transferring data from said redundant memory cells when said normal bit line is replaced by said redundant bit line.
3. The integrated memory according to claim 1 , including: a further redundant sense amplifier; and a further redundant bit line for replacing said normal bit line, said further redundant bit line connected to said data line via said further redundant sense amplifier.
4. The integrated memory according to claim 1 , including: a programmable connection element connecting said line to said normal sense amplifier; and a further programmable connection element connecting said line to said redundant sense amplifier; said programmable connection elements having an electrical conductivity determined by their programming state.
5. The integrated memory according to claim 4 , wherein said programmable connection elements are conductive.
6. The integrated memory according to claim 4 , wherein said programmable connection elements are nonconductive.
7. The integrated memory according to claim 4 , wherein said programmable connection elements are reversibly programmable.
8. The integrated memory according to claim 1 , including: a programmable connection element connecting said normal sense amplifier to said data line; and a further programmable connection element connecting said redundant sense amplifier to said data line; said connection elements having an electrical conductivity depending on their programming state.
9. The integrated memory according to claim 8 , wherein said connection elements are conductive.
10. The integrated memory according to claim 8 , wherein said connection elements are nonconductive.
11. The integrated memory according to claim 8 , wherein said programmable connection elements are reversibly programmable.
12. A method for repairing an integrated memory having normal memory cells, which comprises: providing a normal bit line connected to the normal memory cells for transferring data between the normal memory cells; providing a normal sense amplifier for amplifying data read from the normal memory cells; providing a line connecting the normal sense amplifier to the normal bit line; providing a data line connected to the normal sense amplifier; providing a redundant sense amplifier for replacing the normal sense amplifier in a redundancy situation, the redundant sense amplifier connected to the line and to the data line and amplifying data read from the normal memory cells in the redundancy situation; testing the normal sense amplifier and the normal bit line; if the normal sense amplifier is defective, replacing the normal sense amplifier with the redundant sense amplifier; if at least one of the normal bit line and at least one of the normal memory cells is defective, replacing the bit line with the redundant bit line; writing to and reading from the normal memory cells via the normal sense amplifier to test the normal memory cells of the normal bit line; if the normal memory cells are defective, replacing the normal bit line with the redundant bit line; writing to and reading from the redundant memory cells via the normal sense amplifier to test the redundant memory cells of the redundant bit line; and if the redundant memory cells are defective, reversing the replacement of the normal bit line with the redundant bit line and replacing the normal sense amplifier with the redundant sense amplifier.
13. A method for repairing an integrated memory having normal memory cells, which comprises: providing a normal bit line connected to the normal memory cells for transferring data between the normal memory cells; providing a normal sense amplifier for amplifying data read from the normal memory cells; providing a line connecting the normal sense amplifier to the normal bit line; providing a data line connected to the normal sense amplifier; providing a redundant sense amplifier for replacing the normal sense amplifier in a redundancy situation, the redundant sense amplifier connected to the line and to the data line and amplifying data read from the normal memory cells in the redundancy situation; testing the normal sense amplifier and the normal bit line with the normal memory cells connected thereto; if the normal sense amplifier is defective, replacing the normal sense amplifier with the redundant sense amplifier; if at least one of the normal bit line and at least one of the normal memory cells is defective, replacing the bit line with the redundant bit line; writing to and reading from the normal memory cells via the normal sense amplifier to test the normal memory cells of the normal bit line; if the normal memory cells are defective, replacing the normal sense amplifier with the redundant sense amplifier; writing to and reading from the normal memory cells via the redundant sense amplifier to test the normal memory cells of the normal bit line; and if the normal memory cells remain defective, reversing the replacement of the normal sense amplifier with the redundant sense amplifier by replacing the normal bit line with the redundant bit line.
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June 22, 2001
May 28, 2002
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