In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which a layer including at least a bonding pad section is formed by a damascene method, the method comprising the steps of: (a) forming an opening region 80a for the bonding pad section in an uppermost dielectric layer 22, the opening region being divided by dielectric layers 22a of a specified pattern and including a plurality of partial opening sections 81; (b) successively forming a plurality of conduction layers 820, 840 composed of different materials over the dielectric layer; and (c) removing excess portions of the plurality of conduction layers 820, 840 and the dielectric layer 22 to planarize the plurality of conduction layers and the dielectric layer, to thereby form a bonding pad section 80 in which a plurality of conduction layers 82, 84 composed of different materials are exposed in each of the partial opening sections 81 of the opening region 80a.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a semiconductor device in which at least a layer including a bonding pad section is formed by a damascene method, the method comprising the steps of: (a) forming an opening region for the bonding pad section in an uppermost dielectric layer, the opening region being divided by dielectric layers of a specified pattern and including a plurality of partial opening sections; (b) successively forming a plurality of conduction layers comprising different materials over the dielectric layer; and (c) removing excess portions of the plurality of conduction layers and the dielectric layer to planarize the plurality of conduction layers and the dielectric layer, to thereby form a bonding pad section in which a plurality of conduction layers comprising different materials are exposed in each of the partial opening sections of the opening region.
2. A method for manufacturing a semiconductor device according to claim 1 , wherein, in the step (b), the plurality of conduction layers are formed to a film thickness that allows the plurality of conduction layers to remain after the step (c) of planarization.
3. A method for manufacturing a semiconductor device according to claim 1 , wherein, in the step (a), a wiring groove for an uppermost wiring layer is formed in the uppermost dielectric layer together with the opening region for the bonding pad section.
4. A method for manufacturing a semiconductor device according to claim 3 , wherein, in the step (b), the plurality of conduction layers include a conduction layer for the wiring layer.
5. A method for manufacturing a semiconductor device according to claim 4 , wherein the conduction layer for the wiring layer is a lowermost layer among the plurality of conduction layers and deposited in the wiring groove.
6. A method for manufacturing a semiconductor device according to claim 5 , wherein a conduction layer above the conduction layer for the wiring layer is deposited at least in the opening region for the bonding pad section.
7. A method for manufacturing a semiconductor device according to claim 1 , further comprising, after the step (c), the steps of forming a dielectric protection layer and patterning the dielectric protection layer to have an opening section that exposes the bonding pad section.
8. A method for manufacturing a semiconductor device according to claim 1 , wherein the layer including the bonding pad section is formed by a process selected from the group consisting of a single damascene process and a dual damascene process.
9. A method for manufacturing a semiconductor device according to claim 4 , wherein the conduction layer for the wiring layer is formed from a layer comprising at least one metal selected from aluminum, copper, silver and a metal alloy thereof, and an upper layer above the conduction layer for the wiring layer is formed from a material different from the conduction layer for the wiring layer, and the upper layer is formed from a layer comprising at least one metal selected from aluminum, gold and a metal alloy thereof.
10. A method for manufacturing a semiconductor device according to claim 1 , further comprising, after the step (a), the step of forming at least one of a barrier layer and a cohesion layer over a surface of the opening region for the bonding pad section.
11. A method for manufacturing a semiconductor device according to claim 1 , wherein, in the step (c), the step of planarization is conducted by a chemical-mechanical polishing method.
12. A method for manufacturing a semiconductor device in which at least a layer including a bonding pad section is formed by a damascene method, the method comprising: forming an opening region for the bonding pad section in a dielectric layer, the opening region comprising a plurality of sub-openings divided from one another by dielectric walls; forming a plurality of conduction layers into at least two of the sub-openings; and removing any excess portions of the plurality of conduction layers and the dielectric layer to planarize the plurality of conduction layers and the dielectric layer, to thereby form a bonding pad section in which a plurality of conduction layers are exposed in each of the sub-openings of the opening region.
13. A method for manufacturing a semiconductor device as in claim 12 , wherein the plurality of conduction layers have different compositions.
14. A method for manufacturing a semiconductor device as in claim 12 , wherein a plurality of conduction layers are formed into each of the sub-openings.
15. A method for manufacturing a semiconductor device as in claim 14 , wherein the plurality of conduction layers have different compositions.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 3, 2001
June 4, 2002
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