A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are subdivided into subgroups each of which has four memory cells. A first set of input/output lines is provided for the first group of memory cells, and a second set of input/output lines is provided for the second group of memory cells. An output circuit section is connected to the those sets of input/output lines to output data transferred thereto. An access controller section specifies subgroups alternately from the first and second groups of memory cells with four memory cells as a substantial access minimum unit, accesses memory cells of a specified subgroup to read stored data therefrom and transfers the read data to corresponding input/output lines associated therewith. The read data is supplied to the output circuit section for conversion to serial data and then output therefrom.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A serial-access semiconductor memory device comprising: an array of memory cells, subdivided into a plurality of sections, including first and second sections each of which includes a plurality of subsections each having a preselected number of memory cells, said first and second sections constituting first and second memory banks, respectively; a first address bus section for said first memory bank, said first address bus section coupled to a first decoder connected to said first memory bank; a second address bus section for said second memory bank, said second address bus section coupled to a second decoder connected to said second memory bank; a first data transmission line associated with said first memory bank and connected to respective memory cells of each subsection in said first memory bank; a second data transmission line associated with said second memory bank and connected to respective memory cells of each subsection in said second memory bank; and latch circuits, coupled to said first and second address bus sections, for independently latching address select signals for said each memory banks; wherein said first and second data transmission lines are coupled to read data latches for receiving data bits and transferring the data bits to a data out buffer according to an internal clock associated with an input clock.
2. The device according to claim 1 , further comprising: access controller connected to the first and second address bus sections, for specifying said first and second memory banks in response to a first address signal by randomly selecting one of said subsections in said first memory bank, and for reading data bits which are simultaneously transmitted toward said output section by way of one of the first and second data lines in a parallel manner; and said access controller including address data storage circuit for obtaining and storing therein a second address signal specifying a subsection of said second memory bank while said one first memory bark is being accessed.
3. The device according to claim 1 , further comprising: word lines associated with said array of memory cells, wherein first word lines for the subsections in said first memory bank and second word lines for the subsections in said second memory bank are substantially connected in common.
4. A serial-access semiconductor memory device comprising: an array of memory cells, subdivided into a plurality of sections, including first and second sections each of which includes a plurality of subsections each having a preselected number of memory cells, said first and second sections constituting first and second memory banks, respectively; a first address bus section for said first memory bank, said first address bus section coupled to a first decoder connected to said first memory bank; a second address bus section for said second memory bank, said second address bus section coupled to a second decoder connected to said second memory bank; a first data transmission line associated with said first memory bank and connected to respective memory cells of each subsection in said first memory bank; a second data transmission line associated with said second memory bank and connected to respective memory cells of each subsection in said second memory bank; and latch circuits, coupled to said first and second address bus sections, for independently latching address select signals for said each memory banks; wherein said first and second data transmission lines are coupled to read data latches for receiving data bits and transferring the data bits to a data out buffer according to an internal clock associated with an input clock; and wherein said latch circuits include first and second latch circuits which are associated with said first and second address bus sections respectively.
5. The device according to claim 4 , wherein each of said first and second address storage circuits includes a latch circuit.
6. The device according to claim 2 , wherein said address storage circuit obtains and stores therein an address signal specifying a next subsection of said first memory bank while a corresponding subsection is being accessed in said second memory bank.
7. The device according to claim 2 , further comprising circuit for performing an alternate data transmission using said first data line and said second data line when said first and second data bits are sent from said first and second memory banks toward said read data latches.
8. The device according to claim 2 , wherein said access controller further includes: a set of switching transistors connected between said first data line and said read data latches, said transistors having gate electrodes coupled to a control signal.
9. The device according to claim 2 , further including: a first set of switching transistors connected between said first data lines and said read data latches, said transistors having gate electrodes coupled to a first control signal; and a second set of switching transistors connected between said second data lines and said read data latches, said second set of transistors having gate electrodes coupled to a second control signal.
10. The device according to claim 9 , further including: array of latch circuits having inputs connected to the first and second sets of transistors and an output connected to said read data latches.
11. The device according to claim 10 , wherein said latch circuits are equivalent in number to a number of each of said first and second sets of transistors.
12. A serial-access semiconductor memory device comprising: an array of memory cells being subdivided into a plurality of sections including first and second sections each of which includes a plurality of subsections each having a preselected number, at least one, of memory cells, said first and second sections constituting first and second memory banks, respectively; word lines associated with said array of memory cells, wherein first word lines for the subsections in said first memory bank and second word lines for the subsections in said second memory bank are substantially selected in common; a first address bus section for said first memory bank; a second address bus section for said second memory bank; a first parallel data transmission line associated with said first memory bank and connected to respective memory cells of each subsection in said first memory bank; a second parallel data transmission line associated with said second memory bank and connected to respective memory cells of each subsection in said second memory bank; an output section connected to the first and second data lines and having an output; and access controller coupled to the first and second address bus sections and said output section, for specifying said first and second memory banks, for randomly selecting one of said subsections in said first memory bank and a corresponding one of said subsections in said second memory bank in response to an address signal, and for serially accessing memory cells of said first and second memory banks, first data bits of said first memory bank being transmitted in parallel toward said output section and second data bits of said second memory bank being transmitted in parallel toward said output section; said output section including register for receiving the first data bits and the second data bits and for selecting these first and second data bits to form a series of data bits which will then be sent forth to said output; said access controller including address data storage circuit for storing therein an address signal specifying said corresponding subsection of said second memory bank while said one of said subsections is accessed in said first memory bank; and said address data storage circuit including first and second address storage circuits which are associated with said first and second address bus sections, respectively.
13. The device according to claim 12 , wherein each of said first and second address storage circuits includes a latch circuit.
14. The device according to claim 12 , wherein said first data line and said second data line perform alternate data transmission when said first and second data bits are sent from said first and second memory banks toward said register.
15. The device according to claim 12 , further including: a first set of switching transistors connected between said first data line and said register, said first set of transistors having gate electrodes coupled to a first control signal; and a second set of switching transistors connected between said second data line and said register, said second set of transistors having gate electrodes coupled to a second control signal.
16. The device according to claim 15 , wherein said access controller further includes: an array of latch circuits having inputs connected to the first and second sets of transistors and an output connected to said register.
17. The device according to claim 16 , wherein said latch circuits are equivalent in number to a number of each of said first and second sets of transistors.
18. A serial-access semiconductor memory device comprising: an array of memory cells, subdivided into a plurality of sections, including first and second sections each of which includes a plurality of subsections each having a preselected number of memory cells, said first and second sections constituting first and second memory banks, respectively; a first address bus section for said first memory bank, said first address bus section coupled to a first decoder connected to said first memory bank and a first address storage register which is associated with said first address bus section; a second address bus section for said second memory bank, said second address bus section coupled to a second decoder connected to said second memory bank and a second address storage register which is associated with said second address bus section; a first data transmission line associated with said first memory bank and connected to respective memory cells of each subsection in said first memory bank; a second data transmission line associated with said second memory bank and connected to respective memory cells of each subsection in said second memory bank; and said first and second data transmission lines being coupled to read data latches for receiving data bits and transferring the data bits to a data out buffer according to an internal clock associated with an input clock.
19. A serial-access semiconductor memory device comprising: an array of memory cells, subdivided into a plurality of sections, including a pair of first and second sections each of which includes a plurality of subsections each having a preselected number of memory cells, said first and second sections constituting first and second memory banks, respectively; a first address bus section for said first memory bank; a second address bus section for said second memory bank; first parallel data transmission lines associated with said first memory bank and connected to respective memory cells of each subsection in said first memory bank; second parallel data transmission lines associated with said second memory bank and connected to respective memory cells of each subsection in said second memory bank; an output section connected to the first and second parallel data transmission lines and having an output, said output section including register for receiving first parallel data bits and second parallel data bits and for allowing these first and second parallel data bits to be converted into a series of data bits which will then be sent to said output, and access controller, connected to the first and second address bus sections, for specifying said first and second memory banks in response to a first address signal, said access controller including first and second address data storage circuits for obtaining and storing therein respective first and second address signals, said second address signal specifying a subsection of said second memory bank while said first memory bank is being accessed, said first address signal specifying a subsection of said first memory bank while said second memory bank is being accessed.
20. The device according to claim 19 , further comprising: word lines associated with said array of memory cells, wherein first word lines for the subsections in said first memory bank and second word lines for the subsections in said second memory bank are substantially connected in common.
21. The device according to claim 19 , wherein said address data storage circuit includes first and second address storage circuits which are associated with said first and second address bus sections, respectively.
22. The device according to claim 21 , wherein each of said first and second address storage circuits includes a latch circuit.
23. The device according to claim 19 , further comprising a circuit for performing an alternate data transmission using said first parallel data transmission lines and said second parallel data transmission lines when said first and second data bits are sent from said first and second memory banks toward said register.
24. The device according to claim 19 , further including: a set of switching transistors connected between said first parallel data transmission lines and said register, said transistors having gate electrodes coupled to a control signal.
25. The device according to claim 19 , further including: a first set of switching transistors connected between said first parallel data transmission lines and said register, said first set of transistors having gate electrodes coupled to a first control signal; and a second set of switching transistors connected between said second parallel data transmission lines and said register, said second set of transistors having gate electrodes coupled to a second control signal.
26. The device according to claim 25 , wherein said access controller further includes: an array of latch circuits having inputs connected to the first and second sets of transistors and an output connected to said register.
27. The device according to claim 26 , wherein said latch circuits are equivalent in number to a number of each of said first and second sets of transistors.
28. A semiconductor memory device comprising: an array of memory cells subdivided into at least first and second memory banks; bit lines and word lines electrically coupled to said memory cells, respectively; an address bus section for said first and second memory banks; first data transmission lines independently provided for each of said memory banks; address select lines for selecting said memory cells to transfer data to said first data transmission lines; and address select signal latch circuits coupled to said address bus section, and respectively provided for each of said first and second memory banks.
29. A device according to claim 28 , further comprising: read data latches, coupled to said first data transmission lines for receiving data bits transmitted from said first and second memory banks.
30. A device according to claim 29 , further comprising: second data transmission lines; a bus select circuit for connecting said first data transmission lines to said second data transmission lines; and a data output buffer connected to said second data transmission lines.
31. A device according to claim 30 , further comprising: circuits for receiving a next address, while said latch circuits latch address select signals.
32. The device according to claim 30 , wherein: said read data latches are connected between said bus select circuit and said data output buffer.
33. The device according to claim 30 , wherein said word lines for each of said memory banks are independent.
34. The device according to claim 33 , wherein data included in two adjacent subsections are read out serially.
35. The device according to claim 33 , wherein data included in two adjacent subsections are read out simultaneously to said read data latches, and said data are serially read out from said read data latches according to an internal clock associated with an input clock.
36. A device according to claim 28 , further comprising: circuits for receiving a next address, while said latch circuits latch address select signals.
37. A device according to claim 28 , wherein said word lines for each memory bank are independent.
38. A semiconductor memory device comprising: an array of memory cells subdivided into at least first and second memory banks each of which includes a plurality of subsections; bit lines and word lines electrically coupled to said memory cells; an address bus section for said first and second memory banks; first data transmission lines for connecting respective memory cells of each subsection in said memory banks, said first data transmission lines being provided for each of said memory banks independently; address select lines for selecting said memory cells to transfer data to said first data transmission lines; and latch circuits, coupled to said address bus section and said address select lines, for latching address select signals to receive a next column address without changing a column being accessed, said latch circuits being respectively provided for said first and second memory banks.
39. The device according to claim 38 , wherein data included in two adjacent subsections are read out serially.
40. The device according to claim 38 , wherein data included in two adjacent subsections are read out simultaneously to said read data latches, and said data are serially read out from said read data latches according to an internal clock associated with an input clock.
41. The device according to claim 38 , further comprising: a bus select circuit for connecting said first data transmission lines which are coupled to a data output buffer; and read data latches for receiving data bit transmitted toward said data output buffer, said first data transmission lines being connected to said read data latches via said bus select circuit.
42. A semiconductor memory device comprising: an array of memory cells subdivided into at least first and second memory banks each of which includes a plurality of subsections; bit lines and word lines electrically coupled to said memory cells; an address bus section for said first and second memory banks; first data transmission lines for connecting respective memory cells of each subsection in said memory banks; address select lines for selecting said memory cells to transfer data to said first data transmission lines; latch circuits coupled to said address bus section and said address select lines for latching address select signals, said latch circuits provided for each bank respectively; a bus select circuit for connecting said first data transmission lines to second data transmission lines which are coupled to a data input buffer; and data input latches coupled to said second data transmission lines for receiving data bits from the data input buffer, said data input latches receiving input data from the data input buffer according to an internal clock associated with an input clock.
43. A semiconductor memory device comprising: an array of memory cells subdivided into at least first and second memory banks each of which includes a plurality of subsections; bit lines and word lines electrically coupled to said memory cells; an address bus section for said first and second memory banks; first data transmission lines for connecting respective memory cells of each subsection in said memory banks, said first data transmission lines provided for each of said memory banks respectively; address select lines for selecting said memory cells to transfer data to said first data transmission lines; latch circuits, coupled to said address bus section and said address select lines, for latching address select signals; a bus select circuit for connecting said first data transmission lines to second data transmission lines which are coupled to data output buffer; and read data latches for receiving data bits transmitted from said first and second memory banks, said read data latches holding read data from said first memory bank while receiving an address for said second memory bank into said latch circuits.
44. The device according to claim 43 , wherein data included in adjacent subsections are read out serially.
45. The device according to claim 43 , wherein data included in two adjacent subsections are read out simultaneously to said read data latches according to an internal clock associated with an input clock.
46. A computer system comprising: high speed cache memory; and a main memory connected to said cache memory via a control circuit, said main memory composed of a memory device comprising: an array of memory cells subdivided into at least first and second memory banks; bit lines and word lines electrically coupled to said memory cells; an address bus section for said first and second memory banks; first data transmission lines respectively provided for each of said first and second memory banks; address select lines for selecting said memory cells to transfer data to said first data transmission lines; and address select signal latch circuits coupled to said address bus section and said address select lines, and respectively provided for each of said first and second memory banks.
47. A computer system comprising: high speed cache memory; and a main memory connected to said cache memory via a control circuit, said main memory composed of a memory device comprising: an array of memory cells subdivided into at least first and second memory banks each of which includes a plurality of subsections; bit lines and word lines electrically coupled to said memory cells; an address bus section for said first and second memory banks; first data transmission lines for connecting respective memory cells of each subsection in said memory banks, said first data transmission lines being provided for each of said memory banks respectively; address select lines for selecting said memory cells to transfer data to said first data transmission lines; latch circuits, coupled to said address bus section and said address select lines, for latching address select signals, said latch circuits being respectively provided for said first and second memory banks.
48. A computer system comprising: high speed cache memory; and a main memory connected to said cache memory via a control circuit, said main memory composed of a memory device comprising: an address bus section for first and second memory banks; first data transmission lines for connecting respective memory cells of each subsection in said memory banks, said first data transmission lines being provided for each of said memory banks respectively; address select lines for selecting said memory cells to transfer data to said first data transmission lines; latch circuits, coupled to said address bus section and said address select lines, for latching address select signals; a bus select circuit for connecting said first data transmission lines to second data transmission lines which are coupled to data output buffer; and read data latches for receiving data bits transmitted from said first and second memory banks, said read data latches holding read data from said first memory bank while receiving an address for said second memory bank into said latch circuits.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 31, 2001
June 11, 2002
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.