An electronic device for computing a Fourier transform having a pipeline architecture includes at least one processing stage with a radix equal to 4. Each processing stage includes elementary processing for performing process operations for Fourier transforms of size equal to 4 on data blocks. Each processing stage also includes an elementary storage that includes a random access memory. In particular, the random access memory is a single-access memory with a storage capacity equal to 3N/4 data bits. The size of the data block processed by this stage is equal to N.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device having a pipelined architecture for computing a Fourier transform, the electronic device comprising: at least one processing stage with radix equal to 4 and comprising an elementary processor for performing a Fourier transform of elementary size equal to 4 on data blocks, and an elementary storage circuit comprising a random access memory connected to said elementary process or and having a storage capacity equal to 3N/4 data bits; N being the size of each data block processed by said at least one processing stage.
2. An electronic device according to claim 1 , wherein said random access memory comprises a single-access memory.
3. An electronic device according to claim 1 , wherein said elementary processor respectively performs N/4 butterfly processing operations on N/4 distinct groups of four data bits for each data block processed by said at least one processing stage.
4. An electronic device according to claim 1 , wherein said elementary storage circuit further comprises n registers connected to said random access memory, said random access memory for storing (N/4) (n 1) words of three data bits, each of said n registers for storing 1 word comprising three data bits.
5. An electronic device according to claim 4 , wherein said random access memory comprises a single-access memory.
6. An electronic device according to claim 1 , wherein said at least one processing stage comprises at least one second processing stage comprising: an elementary storage circuit having a storage capacity equal to N data bits, N being the size of each data block processed by said at least one second processing stage; and an elementary processor for determining a dynamic range of a data of each data block processed and for performing a realignment of the data with respect to the determined dynamic range.
7. An electronic device according to claim 6 , wherein said elementary storage circuit comprises: a random access memory; and n registers connected to said random access memory, said random access memory for storing (N/4) (n 1) words of four data bits, each of said n registers for storing 1 word comprising four data bits.
8. An electronic device according to claim 7 , wherein said random access memory comprises a single-access memory.
9. An electronic device according to claim 1 , wherein said at least one processing stage comprises an input for sequentially receiving N data bits of a current data block at a frequency of a first clock signal, the N data bits being ordered within four consecutive segments each comprising N/4 data bits, each datum of a segment forming a group of four data bits together with a counterpart data bit of the other three segments; and wherein said elementary processor comprises an adder/subtracter module for performing at each cycle of the first clock signal a butterfly processing operation on each group of four data bits formed for deriving successive groups of four intermediate data bits respectively ordered within four consecutive intermediate segments, and a multiplier module for multiplying at each cycle of the first clock signal the intermediate data bits by predetermined multiplier coefficients.
10. An electronic device according to claim 9 , further comprising control means for providing to said elementary storage circuit data contained in at least a first three segments of the current data block as the data are received, and for replacing a portion of data stored in said elementary storage circuit by intermediate data contained in a last three intermediate segments, and for redelivering at each cycle of the first clock signal data removed from said elementary storage circuit and data not used by said adder/subtracter module or said multiplier module.
11. An electronic device according to claim 10 , wherein said control means further comprising means for providing to said elementary storage circuit data contained in a first three segments of a current data block as the data are received, and for respectively replacing data stored in said elementary storage circuit by intermediate data contained in a last three intermediate segments as data contained in a fourth segment are received.
12. An electronic device according to claim 10 , wherein said control means further comprises means for providing to said elementary storage circuit data contained in a fourth segment of a current data block as the data are received, and for respectively replacing data contained in a last three segments of the current block stored in said elementary storage circuit by intermediate data contained in a last three intermediate segments as the data contained in a first segment of a next data block are received.
13. An electronic device according to claim 10 , wherein said elementary storage circuit comprises: a first and a second register; and a first and a second controllable multiplexer; wherein said first register is connected to an output of said elementary storage circuit, an output of said first register is connected to an input of said second register by said first controllable multiplexer, the output of said first register is connected to an input of said adder/subtracter module, the output of said first register is connected to an input of said multiplier module by said second controllable multiplexer, said second register is connected to an input of said elementary storage circuit, an output of said adder/subtracter module is connected to the input of said first register by said first multiplexer and to an input of said multiplier module by said second multiplexer.
14. An electronic device according to claim 13 , wherein said control means comprises a first counter modulo N being clocked by the first clock signal for reinitializing on reception of a first datum of each data block, and for controlling said first multiplexer; a second counter modulo N being clocked by the first clock signal for reinitializing on transmission of a first output datum from said at least one processing stage, and for controlling said second multiplexer; and wherein said elementary processor comprises means for addressing said elementary storage circuit comprising a counter modulo N/4 1.
15. An electronic device according to claim 1 , wherein said elementary storage circuit comprising a plurality of distinct elementary memories each having a storage capacity equal to N/4 data bits for storing N/4 words of a datum, N being the size of the data blocks processed by said at least one processing stage, and said distinct elementary memories being selectable and selectively addressable in a read mode and in a write mode.
16. An electronic device according to claim 15 , wherein said elementary storage circuit comprises three distinct elementary memories.
17. An electronic device according to claim 15 , wherein said elementary storage circuit comprises four distinct elementary memories.
18. An electronic device according to claim 15 , wherein each of said at least one processing stage comprises an input for sequentially receiving N data bits of a current data block at a frequency of a first clock signal, the N data bits being ordered within four consecutive segments each comprising N/4 data bits, each datum of a segment forming a group of four data bits together with a counterpart data bit of the other three segments; and wherein said elementary processor comprises an adder/subtracter module for performing at each cycle of the first clock signal a butterfly processing operation on each group of four data bits formed for deriving successive groups of four intermediate data bits respectively ordered within four consecutive intermediate segments, and a multiplier module for multiplying at each cycle of the first clock signal the intermediate data bits by predetermined multiplier coefficients.
19. An electronic device according to claim 18 , further comprising control means for selecting and selectively addressing in a read mode at least one of said elementary memories, and for selecting and selectively addressing in a write mode at least one of said elementary memories, reading and writing being performed at a same address in each of said selected elementary memories to selectively deliver to said elementary memories data contained in at least the first three segments of the current data block as they are received, and respectively and selectively substituting a portion of the stored data of the current data block with the intermediate data contained in the last three intermediate segments.
20. An electronic device according to claim 19 , wherein said control means comprises a first counter modulo N being clocked by the first clock signal for reinitializing on reception of a first datum of each data block; a second counter modulo N being clocked by the first clock signal for reinitializing on transmission of a first output datum from said at least one processing stage, a value of said first counter module determines which of said elementary memories are to be selected and addressed in a write mode while a value of the second counter modulo determines which of said elementary memories are to be selected and addressed in a read mode.
21. An electronic device according to claim 20 , wherein said control means further comprises two multiplexers; and wherein said first counter modulo N controls said first multiplexer and said second counter modulo N controls said second multiplexer.
22. An electronic device according to claim 21 , wherein said elementary processor comprises means for addressing said elementary memories comprising a counter modulo N/4 having a value defining a write and/or a read address in at least one of said selected elementary memories; and wherein said control means comprises means for storing the write address on reception of the first datum from each current data block and for reusing the write address address when the value of the first counter reaches 3N/4 data bits.
23. An electronic device according to claim 19 , wherein said elementary storage circuit comprising: a first and a second register; and a first and a second controllable multiplexer; wherein said first register is connected to the output of said elementary memories, an output of said first register is connected to an input of said second register by said first controllable multiplexer, the output of said first register is connected to an input of said adder/subtracter module, the output of said first register is connected to an input of said multiplier module by said second controllable multiplexer, said second register is connected to an input of said elementary memories, an output of said adder/subtracter module is connected to the input of said first register by said first multiplexer and to the input of said multiplier module by said second multiplexer.
24. An electronic device having a pipelined architecture for computing a Fourier transform, the electronic device comprising: at least one first processing stage with radix equal to 4 and comprising an elementary processor for performing a Fourier transform of elementary size equal to 4 on received data blocks, wherein said elementary processor respectively performs N/4 butterfly processing operations on N/4 distinct groups of four data bits for each data block, and an elementary storage circuit having a storage capacity equal to 3N/4 data bits, N being the size of each data block processed by said at least one first processing stage, said elementary storage circuit comprising a random access memory.
25. An electronic device according to claim 24 , wherein said random access memory comprises a single access memory, and wherein said elementary storage circuit further comprises n registers connected to said single access memory, said single access memory for storing (N/4) (n 1) words of three data bits, each of said n registers for storing 1 word comprising three data bits.
26. An electronic device according to claim 24 , wherein said at least one first processing stage comprises an input for sequentially receiving N data bits of a current data block at a frequency of a first clock signal, the N data bits being ordered within four consecutive segments each comprising N/4 data bits, each datum of a segment forming a group of four data bits together with a counterpart data bit of the other three segments; and wherein said elementary processor comprises an adder/subtracter module for performing at each cycle of the first clock signal a butterfly processing operation on each group of four data bits formed for deriving successive groups of four intermediate data bits respectively ordered within four consecutive intermediate segments, and a multiplier module for multiplying at each cycle of the first clock signal the intermediate data bits by predetermined multiplier coefficients.
27. An electronic device according to claim 26 , further comprising control means for providing to said elementary storage circuit data contained in a first three segments of a current data block as the data are received, and for respectively replacing data stored in said elementary storage circuit by intermediate data contained in a last three intermediate segments as data contained in a fourth segment are received.
28. An electronic device according to claim 27 , wherein said elementary storage circuit comprises: a first and a second register; and a first and a second controllable multiplexer; wherein said first register is connected to an output of said elementary storage circuit, an output of said first register is connected to an input of said second register by said first controllable multiplexer, the output of said first register is connected to an input of said adder/subtracter module, the output of said first register is connected to an input of said multiplier module by said second controllable multiplexer, said second register is connected to an input of said elementary storage circuit, an output of said adder/subtracter module is connected to the input of said first register by said first multiplexer and to an input of said multiplier module by said second multiplexer.
29. An electronic device according to claim 28 , wherein said control means comprises a first counter modulo N being clocked by the first clock signal for reinitializing on reception of a first datum of each data block, and for controlling said first multiplexer; a second counter modulo N being clocked by the first clock signal for reinitializing on transmission of a first output datum from said at least one first processing stage, and for controlling said second multiplexer; and wherein said elementary processor comprises means for addressing said elementary storage circuit comprising a counter modulo N/4 1.
30. An electronic device having a pipelined architecture for computing a Fourier transform, the electronic device comprising: at least one second processing stage with radix equal to 4 and comprising an elementary processor for performing a Fourier transform of elementary size equal to 4 on received data blocks, wherein said elementary processor respectively performs N/4 butterfly processing operations on N/4 distinct groups of four data bits for each data block, and for determining a dynamic range of a data bit of each data block processed and for performing a realignment of the data with respect to the determined dynamic range, and an elementary storage circuit having a storage capacity equal to N data bits, N being the size of each data block processed by said at least one second processing stage, said elementary storage circuit comprising a random access memory.
31. An electronic device according to claim 30 , wherein the random access memory comprises a single access memory; and wherein said elementary storage circuit further comprises n registers connected to said single access memory, said single access memory for storing (N/4) (n 1) words of four data bits, each of said n registers for storing 1 word comprising four data bits.
32. An electronic device according to claim 30 , wherein said at least one second processing stage comprises an input for sequentially receiving N data bits of a current data block at a frequency of a first clock signal, the N data bits being ordered within four consecutive segments each comprising N/4 data bits, each datum of a segment forming a group of four data bits together with a counterpart data bit of the other three segments; and wherein said elementary processor comprises an adder/subtracter module for performing at each cycle of the first clock signal a butterfly processing operation on each of group of four data bits formed for deriving successive groups of four intermediate data bits respectively ordered within four consecutive intermediate segments, and a multiplier module for multiplying at each cycle of the first clock signal the intermediate data bits by predetermined multiplier coefficients.
33. An electronic device according to claim 32 , further comprising control means for providing to said elementary storage circuit data contained in a fourth segment of a current data block as the data bits are received, and for respectively replacing data contained in a last three segments of the current block stored in said elementary storage circuit by intermediate data bits contained in a last three intermediate segments as the data bits contained in a first segment of a next data block are received.
34. An electronic device according to claim 33 , wherein said elementary storage circuit comprises: a first and a second register; and a first and a second controllable multiplexer; wherein said first register is connected to an output of said elementary storage circuit, an output of said first register is connected to an input of said second register by said first controllable multiplexer, the output of said first register is connected to an input of said adder/subtracter module, the output of said first register is connected to an input of said multiplier module by said second controllable multiplexer, an output of said adder/subtracter module is connected to the input of said first register by said first multiplexer and to an input of said multiplier module by said second multiplexer.
35. An electronic device according to claim 34 , wherein said control means comprises a first counter modulo N being clocked by the first clock signal for reinitializing on reception of a first datum of each data block, and for controlling said first multiplexer; and a second counter modulo N being clocked by the first clock signal for reinitializing on transmission of a first output datum from said at least one second processing stage, and for controlling said second multiplexer; and wherein said elementary processor comprises means for addressing said elementary storage circuit comprising a counter modulo N/4 1.
36. A method for controlling a radix 4 processing stage of a device having a pipelined architecture for computing a Fourier transform, the method comprising the steps of: receiving at least one data block comprising N data bits; storing 3N/4 data bits of the at least one data block in a random access memory; and performing a Fourier transform of elementary size equal to 4 on at least one data block.
37. A method according to claim 36 , wherein the processing stage has an input for sequentially receiving the N data bits of the at least one data block and orders the N data bits within four consecutive segments, each segment comprising N/4 data bits and each datum of a segment forming a group of four data bits together with a counterpart data bit of the other three segments; and wherein the storing comprises storing data contained in a first three segments in the random access memory as the N data bits are received; and wherein the processing comprises processing the group of four data bits using a butterfly operation responsive to receiving data for the fourth segment for deriving successive groups of four intermediate data bits respectively ordered within four consecutive intermediate segments, and replacing data stored in the random access memory by a respective intermediate data contained in a last three intermediate segments.
38. A method according to claim 36 , wherein the random access memory comprises a single-access memory.
39. A method for controlling a radix 4 processing stage of a device having pipelined architecture for computing a Fourier transform, the method comprising the steps of: receiving at least one data block comprising N data bits; storing N data bits of the at least one data block in a random access memory; performing a Fourier transform of elementary size equal to 4 on the at least one data block; determining a dynamic range of a data bit of each data block processed; and performing a realignment of the data with respect to the determined dynamic range.
40. A method according to claim 39 , wherein the processing stage has an input for sequentially receiving the N data bits of the at least one data block, and orders the N data bits within four consecutive segments, each segment comprising N/4 data bits, each datum of a segment forming a group of four data bits together with a counterpart data bit of the other three segments; and wherein the storing comprise s storing data contained in a fourth segment in the random access memory as the data are received; and wherein the processing comprises processing the group of four data bits using a butterfly operation, and replacing data stored in a first segment of a next data block received, and respectively replacing data contained in a last three segments of a current block stored in the random access memory by intermediate data contained in a last three intermediate segments.
41. A method according to claim 39 , wherein the random access memory comprises a single-access memory.
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December 18, 1998
June 18, 2002
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