Cache coherency protocol having an imprecise hovering (H) state for instructions and data

1. A method of maintaining cache coherency in a data processing system including a plurality of processors that are each associated with a respective one of a plurality of caches and an interconnect coupling said processors, said method comprising: in a first cache among said plurality of caches, storing a first data item in association with an address tag indicating an address of said first data item and setting a coherency indicator in said first cache to a data-invalid state that indicates that said address tag is valid and that said first data item in said first cache is invalid; and in response to subsequent detection of a data transfer on said interconnect associated with said address indicated by said address tag, said data transfer being initiated by another of said plurality of caches and including a second data item, selectively updating said first cache with said second data item only if a number of updates to said first cache pending within a queue of a cache controller of said first cache is less than a threshold number, wherein selectively refreshing said first cache includes said cache controller (1) temporarily allocating an entry of said queue, (2) replacing said first data item by storing said second data item in said first cache in association with said address tag, and (3) updating said coherency indicator from said data-invalid state to a valid state to indicate that said second data item is valid.

2. The method of claim 1 , wherein said step of updating said coherency indicator to a valid state comprises updating said coherency indicator to a shared state that indicates that said second data item is stored in both said first cache and another of said plurality of caches.

3. The method of claim 1 , wherein said method further comprises setting the coherency indicator in said first cache to one of modified state, shared state, and exclusive state; and thereafter performing said setting step in response to snooping a data invalidate transaction on the interconnect.

4. The method of claim 5 , wherein snooping said data invalidation transaction comprises said first cache snooping a read-with-intent-to-modify transaction on said interconnect.

5. The method of claim 1 , wherein said plurality of processors includes a first processor associated with said first cache and a second processor associated with a second cache among said plurality of caches, said method further comprising the step of: in response to a request by said first processor for data associated with said address indicated by said address tag while said coherency indicator is set to said second state, sourcing a data transfer including said second data item from said second cache.

6. The method of claim 1 , and further comprising initiating said data transfer by said another of said plurality of caches by issuing a read-type request.

7. A cache for supporting cache coherency in a data processing system including a plurality of processors that are each associated with a respective one of a plurality of caches and an interconnect coupling said plurality of processors, said cache comprising: data storage; tag storage that stores an address tag indicating an address of a data item contained in said data storage; a coherency indicator having one or more valid states to indicate that an associated data item in said data storage is valid and a data-invalid state to indicate that said address tag in said tag storage is valid and that a data item in said data storage is invalid; and a cache controller including a queue from which said cache controller updates said cache, wherein responsive to detection of a data transfer on said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said data-invalid state, said data transfer including a second data item, said cache controller selectively updating said cache with said second data item only if a number of updates pending in said queue is less than a threshold number by (1) temporarily allocating an entry of said queue, (2) storing said second data item in said data storage in association with said address tag and (3) updating said coherency indicator to one of said one or more valid states.

8. The cache of claim 7 , wherein said one or more valid states include a shared state to which said cache controller updates said coherency indicator when updating said cache to indicate that said second data item is stored in both said cache and another of said plurality of caches.

9. The cache of claim 7 , wherein said cache is a first cache and said plurality of processors includes a first processor associated with said first cache, said cache controller further comprising: means, responsive to a request by said first processor for data associated with said address indicated by said address tag while said coherency indicator is set to said data-invalid state, for requesting valid data associated with said address from one of said plurality of caches associated with a processor among said plurality of processors other than said first processor.

10. The cache of claim 7 , said coherency indicator further comprising an invalid state that indicates that both of said address tag and said first data item are invalid.

11. The cache of claim 7 , wherein said data transfer comprises a response to a read-type request on said interconnect.

12. A data processing system, comprising: an interconnect; a plurality of processors coupled to said interconnect; a plurality of caches that are each associated with a respective one of said plurality of processors, wherein a first cache among said plurality of caches includes: data storage; tag storage that stores ah address tag indicating an address of a data item contained in said data storage; a coherency indicator having one or more valid states to indicate that an associated data item in said data storage is valid and a data-invalid state to indicate that said address tag in said tag storage is valid and that a data item in said data storage is invalid; and a cache controller including a queue from which said cache controller updates said cache, wherein responsive to detection of a data transfer on said interconnect associated with said address indicated by said address tag while said coherency indicator is set to said data-invalid state, said data transfer including a second data item, said cache controller selectively updating said first cache with said second data item only if a number of undates pending in said queue is less than a threshold number by (1) temporarily allocating an entry of said queue, (2) storing said second data item in said data storage in association with said address tag and (3) updating said coherency indicator to one of said one or more valid states.

13. The data processing system of claim 12 , wherein said one or more valid states include a shared state to which said cache controller updates said coherency indicator when updating said cache to indicate that said second data item is stored in both said first cache and another of said plurality of caches.

14. The data processing system of claim 12 , wherein said plurality of processors includes a first processor associated with said first cache, said cache controller further comprising: means, responsive to a request by said first processor for data associated with said address indicated by said address tag while said coherency indicator in said first cache is set to said data-invalid state, for requesting valid data associated with said address from one of said plurality of caches associated with a processor among said plurality of processors other than said first processor.

15. The data processing system of claim 12 , said coherency indicator further comprising an invalid state that indicates that both of said address tag and said first data item are invalid.

16. The data processing system of claim 12 , wherein said data transfer comprises a response to a read-type request on said interconnect.