An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit. The chaining bit is used to “chain” instructions appearing after the last instruction of the last issue group of a first VLIW packet to the instructions in the first issue group of a second VLIW packet. In one embodiment, a mask generation logic along with other logic blocks are utilized to generate an appropriate mask. The generated mask is used to pass through instructions in a VLIW packet which belong to a same issue group for execution in a same clock cycle.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A processor comprising: a first plurality of instructions in a packet of instructions in said processor; an issue group in said packet; a template in said packet, said template including an end marker; said end marker identifying a second plurality of said instructions in said packet, said issue group comprising said second plurality of said instructions, said second plurality being equal to or less than said first plurality.
2. The processor of claim 1 wherein said first plurality is equal to seven.
3. The processor of claim 1 wherein said packet comprises at least 128 bits and each of said first plurality of instructions comprises at least 16 bits.
4. The processor of claim 1 wherein said end marker comprises at most three bits.
5. The processor of claim 1 wherein said second plurality is equal to seven.
6. A processor comprising: a first plurality of instructions in a packet of instructions in said processor; at most three issue groups in said packet; a template in said packet, said template having at least one end marker, said at least one end marker dividing said first plurality of instructions into said at most three issue groups, wherein each of said at most three issue groups comprises at least one of said first plurality of instructions.
7. The processor of claim 6 wherein said first plurality is equal to seven.
8. The processor of claim 6 wherein said template in said packet has two end markers.
9. The processor of claim 6 wherein said template in said packet has three end markers.
10. The processor of claim 6 wherein said packet comprises at least 128 bits and each of said first plurality of instructions comprises at least 16 bits.
11. The processor of claim 6 wherein said at least one end marker comprises at most three bits.
12. A processor comprising: a first plurality of instructions in a packet of instructions in said processor; a template in said packet, said template comprising a plurality of end markers; a mask generation logic, said mask generation logic generating a first mask during a first clock cycle, said first mask corresponding to a first one of said plurality of end markers in said template; said first mask selecting a second plurality of instructions in said packet, said second plurality being less than or equal to said first plurality, said second plurality of instructions belonging to a first issue group.
13. The processor of claim 12 wherein said mask generation logic generates a second mask in a second clock cycle, said second mask corresponding to a second one of said plurality of end markers in said template; said second mask selecting a third plurality of instructions in said packet, said third plurality being less than or equal to said first plurality, said third plurality of instructions belonging to a second issue group.
14. The processor of claim 12 wherein said mask generation logic generates a third mask in a third clock cycle, said third mask corresponding to a third one of said plurality of end markers in said template; said third mask selecting a fourth plurality of instructions in said packet, said fourth plurality being less than or equal to said first plurality, said fourth plurality of instructions belonging to a third issue group.
15. The processor of claim 12 wherein said first plurality is equal to seven.
16. The processor of claim 12 wherein said packet comprises at least 128 bits and each of said first plurality of instructions comprises at least 16 bits.
17. The processor of claim 12 wherein each of said plurality of end markers comprises at most three bits.
18. A method comprising the steps of: providing a plurality of end markers in a template in a packet of instructions in a processor; dividing a first plurality of instructions in said packet into at most three issue groups, each of said at most three issue groups being identified by said plurality of end markers.
19. The method of claim 18 wherein said first plurality of instructions comprises seven instructions.
20. The method of claim 18 wherein said plurality of end markers comprises two end markers.
21. The method of claim 18 wherein said plurality of end markers comprises three end markers.
22. The method of claim 18 wherein said packet comprises at least 128 bits and each of said first plurality of instructions comprises at least 16 bits.
23. The method of claim 18 wherein each of said plurality of end markers comprises at most three bits.
24. A processor comprising: a first plurality of instructions in a packet of instructions in said processor; a second plurality of issue groups in said packet, said second plurality being less than said first plurality; each of said second plurality of issue groups comprising at least one of said first plurality of instructions; each of said first plurality of instructions belonging to one of said second plurality of issue groups; wherein said packet comprises a template having a plurality of end markers, said plurality of end markers identifying each of said second plurality of issue groups in said packet.
25. The processor of claim 24 wherein each of said plurality of end markers comprises at most three bits.
26. The processor of claim 24 wherein said plurality of end markers comprises two end markers and wherein said two end markers identify each of said second plurality of issue groups in said packet.
27. The processor of claim 26 wherein each of said two end markers comprises at most three bits and wherein said second plurality of issue groups comprises three issue groups.
28. A processor comprising: a first plurality of instructions in a first packet of instructions in said processor; a second plurality of instructions in a second packet of instructions in said processor; a first packet template, said first packet template including a chaining bit; said chaining bit causing a third plurality of instructions in said first packet and a fourth plurality of instructions in said second packet to be placed in a combined issue group; wherein said first packet template includes a plurality of first packet end markers, said plurality of first packet end markers identifying at most three first packet issue groups.
29. The processor of claim 28 further comprising a second packet template, wherein said second packet template includes a plurality of second packet end markers, said plurality of said packet end markers identifying at most three second packet issue groups.
30. The processor of claim 28 wherein each of said plurality of first packet end markers comprises at most three bits.
31. The processor of claim 29 wherein each of said plurality of second packet end markers comprises at most three bits.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 16, 2000
July 2, 2002
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