A process is disclosed which inhibits cracking of the layer of low k silicon oxide dielectric material on an integrated circuit structure during subsequent processing of the layer of low k silicon oxide dielectric material. The process comprises: forming a layer of low k silicon oxide dielectric material on an integrated circuit structure on a semiconductor substrate, and forming over the layer of low k silicon oxide dielectric material a capping layer of dielectric material having: a dielectric constant not exceeding about 4, a thickness of at least about 300 nm, and a compressive stress of at least about 3×109 dynes/cm2. In a preferred embodiment, the capping layer comprises silicon oxide formed by reaction of silane and N2O in a PECVD process carried out within a pressure range of from about 600 milliTorr to about 1000 milliTorr; and a temperature range of from about 300° C. to about 400° C.; while maintaining a plasma at a power level ranging from about 250 watts to about 350 watts; a flow of silane equivalent to a flow of from about 35 sccm to about 45 sccm into a 10 liter reactor; and a flow of N2O equivalent to a flow of from about 3800 sccm to about 4200 sccm into the 10 liter reactor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A process which inhibits cracking of a layer of low k silicon oxide dielectric material on an integrated circuit structure during subsequent processing of said layer of low k silicon oxide dielectric material which comprises: a) forming a layer of low k silicon oxide dielectric material on an integrated circuit structure on a semiconductor substrate; and b) forming over said layer of low k silicon oxide dielectric material a capping layer of dielectric material having: 1) a dielectric constant not exceeding about 4; 2) a thickness of at least about 300 nm; and 3) a compressive stress of at least about 3 10 9 dynes/cm 2 .
2. The process of claim 1 wherein said capping layer thickness ranges from about 300 nm to about 400 nm.
3. The process of claim 1 wherein said capping layer has a compressive stress greater than 3 10 9 dynes/cm 2 .
4. The process of claim 1 wherein said capping layer has a compressive stress ranging from about 3 10 9 dynes/cm 2 to about 4 10 9 dynes/cm 2 .
5. The process of claim 1 wherein said capping layer comprises silicon oxide.
6. The process of claim 5 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process.
7. The process of claim 6 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out within a pressure range of from about 600 milliTorr to about 1000 milliTorr.
8. The process of claim 6 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out within a temperature range of from about 300 C. to about 400 C.
9. The process of claim 6 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out while maintaining a plasma at a power level ranging from about 250 watts to about 350 watts.
10. The process of claim 6 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out while maintaining a flow of silane equivalent to a flow of from about 35 sccm to about 45 sccm into a 10 liter reactor.
11. The process of claim 6 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out while maintaining a flow of N 2 O equivalent to a flow of from about 3800 sccm to about 4200 sccm into a 10 liter reactor.
12. The process of claim 6 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out within a pressure range of from about 600 milliTorr to about 1000 milliTorr; and a temperature range of from about 300 C. to about 400 C.; while maintaining a plasma at a power level ranging from about 250 watts to about 350 watts; a flow of silane equivalent to a flow of from about 35 sccm to about 45 sccm into a 10 liter reactor; and a flow of N 2 O equivalent to a flow of from about 3800 sccm to about 4200 sccm into said 10 liter reactor.
13. The process of claim 12 wherein said process for forming said silicon oxide capping layer is carried out for a period of time equivalent to at least about 80 seconds for a 200 mm diameter wafer to form said capping layer to a thickness of at least about 300 nm.
14. The process of claim 1 wherein said first and second steps are carried out without exposing said semiconductor substrate to the atmosphere between said steps.
15. A process which inhibits cracking of said layer of low k silicon oxide dielectric material on an integrated circuit structure during subsequent processing of said layer of low k silicon oxide dielectric material which comprises: a) forming in a first chamber of an apparatus a layer of low k silicon oxide dielectric material on an integrated circuit structure on a semiconductor substrate; b) transferring said substrate to a second chamber in said apparatus without exposing said layer of low k silicon oxide dielectric material to the atmosphere; and c) forming in said second chamber over said layer of low k silicon oxide dielectric material a capping layer of silicon oxide dielectric material having: 1) a dielectric constant not exceeding about 4; 2) a thickness of at least about 300 nm; and 3) a compressive stress of at least about 3 10 9 dynes/cm 2 .
16. The process of claim 15 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out within a pressure range of from about 700 milliTorr to about 900 milliTorr.
17. The process of claim 15 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out within a temperature range of from about 325 C. to about 375 C.
18. The process of claim 15 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out while maintaining a plasma at a power level ranging from about 275 watts to about 325 watts.
19. The process of claim 15 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out while maintaining a flow of silane equivalent to a flow of from about 35 sccm to about 45 sccm into a 10 liter reactor, and a flow of N 2 O equivalent to a flow of from about 3800 sccm to about 4200 sccm into said 10 liter reactor.
20. The process of claim 15 wherein said silicon oxide capping layer is formed by reaction of silane and N 2 O in a PECVD process carried out within a pressure range of from about 700 milliTorr to about 900 milliTorr; and a temperature range of from about 325 C. to about 375 C.; while maintaining a plasma at a power level ranging from about 275 watts to about 325 watts; a flow of silane equivalent to a flow of from about 35 sccm to about 45 sccm into a 10 liter reactor; and a flow of N 2 O equivalent to a flow of from about 3800 sccm to about 4200 sccm into said 10 liter reactor.
21. A process which inhibits cracking of a layer of low k silicon oxide dielectric material on an integrated circuit structure during subsequent processing of said layer of low k silicon oxide dielectric material which comprises: a) forming in a first chamber of an apparatus a layer of low k silicon oxide dielectric material on an integrated circuit structure on a semiconductor substrate; b) transferring said substrate to a second chamber in said apparatus without exposing said layer of low k silicon oxide dielectric material to the atmosphere; and c) forming in said second chamber over said layer of low k silicon oxide dielectric material a capping layer of silicon oxide dielectric material by reaction of silane and N 2 O in a PECVD process carried out within a pressure range of from about 700 milliTorr to about 900 milliTorr; and a temperature range of from about 325 C. to about 375 C.; while maintaining a plasma at a power level ranging from about 275 watts to about 325 watts; a flow of silane equivalent to a flow of from about 35 sccm to about 45 sccm into a 10 liter reactor; and a flow of N 2 O equivalent to a flow of from about 3800 sccm to about 4200 sccm into said 10 liter reactor; whereby a capping layer of silicon oxide will be formed over said layer of low k silicon oxide dielectric material capable of inhibiting cracking of said layer of low k silicon oxide dielectric material during subsequent annealing of said substrate, said capping layer having: a) a dielectric constant not exceeding about 4; b) a thickness of at least about 300 nm; and c) a compressive stress of at least about 3 10 9 dynes/cm 2 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 1, 2000
July 16, 2002
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