A field effect transistor (T) of the (quasi-)vertical type, which means that in the semiconductor body (10) of the transistor (T), a source (1) and a drain (3) are positioned (approximately) above each other and are separated from each other by the channel region (2), which is connected to a gate region (4), each one of said regions being connected to a connection conductor (6, 7, 11) joining a connection region (7, 8, 12). The connection regions (7, 8) of the source (1) and the gate (4) are situated on top of the semiconductor body (10). The semiconductor body (10) is provided with a through-hole (9) at least one wall of which is covered with a conductive layer (11), which is connected to the drain (3), and which forms the connection conductor (11) of the drain (3) and which is connected to the connection region (12) for the drain (3) situated on top of the semiconductor body (10). In this way, the transistor (T) is very well suited for surface mounting and is also very easy to manufacture. The through-hole (9) can be made by means of a cheap technique, such as laser cutting or sandblasting. Moreover, the transistor (T) is insensitive to the thickness of the channel region (2), which, in addition, may be comparatively thick. This simplifies the manufacture thereof and renders the transistor (T) suitable for both high power and high voltage applications. An additional advantage is that the transistor (T) can be manufactured without using a comparatively expensive epitaxial process.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device having a field effect transistor (T) and comprising a semiconductor body ( 10 ) having a stack of, in succession and viewed from the upper surface of the semiconductor body ( 10 ), a first semiconductor region ( 1 ) of a first conductivity type, which forms a source ( 1 ) of the transistor (T) and is provided with a first connection conductor ( 5 ), a second semiconductor region ( 2 ) of a second, opposite conductivity type, and a third semiconductor region ( 3 ) of the first conductivity type, which forms a drain ( 3 ) of the transistor (T) and is provided with a second connection conductor ( 11 ), and a gate ( 4 ) which laterally adjoins the second semiconductor region ( 2 ), by means of which gate a current can be sent between the first and the third semiconductor region ( 1 , 3 ) and through the second semiconductor region ( 2 ), and which comprises a gate electrode ( 6 ), with the first connection conductor ( 5 ) and the gate electrode ( 6 ) being connected to, respectively, a first and a second connection region ( 7 , 8 ) situated on the upper surface of the semiconductor body ( 10 ), characterized in that the semiconductor body ( 10 ) is provided with a through-hole ( 9 ) at least one wall of which is covered with a conductive layer ( 11 ), which is connected to the third semiconductor region ( 3 ) and which forms the second connection conductor ( 11 ) and is connected to a third connection region ( 12 ) situa semiconductor body ( 10 ).
2. A semiconductor device as claimed in claim 1 , characterized in that the connection regions ( 7 , 8 , 12 ) on the upper surface are provided with means ( 14 ) for surface mounting the semiconductor body ( 10 ), said means preferably comprising an array of spherical conductors ( 14 ).
3. A semiconductor device as claimed in claim 1 , characterized in that the second semiconductor region ( 2 ) comprises a semiconductor substrate ( 2 ) wherein, at the upper side and the lower side, respectively, the first and the third semiconductor region ( 1 , 3 ) are formed by means of diffusion or ion implantation.
4. A semiconductor device as claimed in claim 1 , 2 or 3 , characterized in that the through-hole ( 9 ) is round.
5. A semiconductor device as claimed in claim 1 , characterized in that the through-hole ( 9 ) is slit-shaped.
6. A semiconductor device as claimed in claim 5 , characterized in that the through-hole ( 9 ) is situated at the location of a scratch or saw path ( 15 ) next to the transistor (T), and the conductive layer ( 11 ) is situated on the two walls of the through-hole ( 9 ) which extend in the longitudinal direction of said through-hole ( 9 ).
7. A semiconductor device as claimed in claim 1 , characterized in that the parts of the second semiconductor region ( 2 ) adjoining the walls of the through-hole ( 9 ) are of the first conductivity type or are covered with an insulating layer ( 20 ).
8. A support plate provided with a conductor pattern on which a semiconductor device as claimed in claim 1 is situated, the connection regions ( 7 , 8 , 12 ) on the upper surface of the semiconductive body ( 10 ) being electrically connected to the conductor pattern.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 10, 2000
July 16, 2002
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