A dynamic random access memory (DRAM) circuit and its associated sub-word-line driver. The DRAM circuit includes a boost circuit, a main word line driver and a sub-word line driver. The boost circuit changes its output boost voltage, which lies between an internal supply voltage and an operating voltage, according to an input row access strobe (RAS) signal. The main word line driver is connected to the output terminal of the boost circuit and the main word line, selected according to input address decoding, is driven by the boost voltage. The sub-word line driver is connected to the main word line. An even or odd sub-word-line signal is generated according to the least significant bit of an input address so that voltage level on the main word line can be used to drive the corresponding sub-word line.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A dynamic random access memory (DRAM) circuit, comprising: a boost circuit for outputting a boost voltage, wherein voltage level of the boost voltage changes according to an input row access strobe (RAS) signal, and voltage level of the boost voltage lies between an internal supply voltage and an operating voltage; a main word line driver coupled to the output terminal of the boost circuit, wherein the selection of one of the main word lines is driven by the boost voltage according to the result of decoding an input address; and a sub-word line driver coupled to the main word line, wherein the sub-word line is driven by the voltage on the main word line according to an even/odd sub-word-line signal generated by the decoded least significant bit of an input address.
2. The DRAM circuit of claim 1 , wherein the boost circuit further includes: a voltage-boosting capacitor for pushing voltage level of the boost voltage to the operating voltage level according to input RAS signal; and a voltage pre-charging transistor for pushing voltage level of the boost voltage to a level identical to the internal supply voltage according to input RAS signal.
3. The DRAM circuit of claim 2 , wherein the voltage-boosting capacitor is used to push voltage level of the boost voltage when the RAS signal is at a high potential and the voltage pre-charging transistor is used to push voltage level of the boost voltage when the RAS signal is at a low potential.
4. The DRAM circuit of claim 1 , wherein the sub-word line driver further includes: a first relay transistor and a second relay transistor, wherein the source/drain terminals of the first relay transistor are connected to a main word line and an even sub-word line, the gate terminal of the first relay transistor is connected to an odd sub-word line, the source/drain terminals of the second relay transistor are connected to the main word line and the odd sub-word line, and the gate terminal of the second relay transistor is connected to the even sub-word line; a first pull-down transistor and a second pull-down transistor, wherein the source/drain terminals of the first pull-down transistor are connected to the even sub-word line and a reference voltage point, the gate terminal of the first pull-down transistor is connected to a terminal for receiving an even sub-word-line signal, the source/drain terminals of the second pull-down transistor are connected to the odd sub-word line and the reference voltage point, and the gate terminal of the second pull-down transistor is connected to a terminal for receiving an odd sub-word-line signal; and a first pass transistor and a second pass transistor, wherein the source/drain terminals of the first pass transistor are connected to the main word line and the even sub-word line, the gate terminal of the first pass transistor is connected to the terminal for receiving the odd sub-word-line signal, the source/drain terminals of the second pass transistor are connected to the main word line and the odd sub-word line, and the gate terminal of the second pass transistor is connected to the terminal for receiving the even sub-word-line signal.
5. The DRAM circuit of claim 4 , wherein the even sub-word line and the odd sub-word line are each coupled to at least one memory cell.
6. A dynamic random access memory (DRAM) circuit, comprising: a boost circuit that includes a voltage-boosting capacitor and a voltage pre-charging transistor, wherein the voltage-boosting capacitor pushes voltage level of the boost voltage to an operating voltage level according to input RAS signal and the voltage pre-charging transistor pushes voltage level of the boost voltage to a level identical to an internal supply voltage according to input RAS signal; a main word line driver coupled to the output terminal of the boost circuit, wherein the selection of one of the main word lines is driven by the boost voltage according to the result of decoding an input address; and a sub-word line driver coupled to the main word line comprising of a first relay transistor, a second relay transistor, a first pull-down transistor, a second pull-down transistor, a first pass transistor and a second pass transistor, wherein a first relay transistor and a second relay transistor, wherein the source/drain terminals of the first relay transistor are connected to a main word line and an even sub-word line, the gate terminal of the first relay transistor is connected to an odd sub-word line, the source/drain terminals of the second relay transistor are connected to the main word line and the odd sub-word line, and the gate terminal of the second relay transistor is connected to the even sub-word line; the source/drain terminals of the first pull-down transistor are connected to the even sub-word line and a reference voltage point, the gate terminal of the first pull-down transistor is connected to a terminal for receiving an even sub-word-line signal, the source/drain terminals of the second pull-down transistor are connected to the odd sub-word line and the reference voltage point, and the gate terminal of the second pull-down transistor is connected to a terminal for receiving an odd sub-word-line signal; the source/drain terminals of the first pass transistor are connected to the main word line and the even sub-word line, the gate terminal of the first pass transistor is connected to the terminal for receiving the odd sub-word-line signal, the source/drain terminals of the second pass transistor are connected to the main word line and the odd sub-word line, and the gate terminal of the second pass transistor is connected to the terminal for receiving the even sub-word-line signal.
7. The DRAM circuit of claim 6 , wherein the voltage-boosting capacitor is used to push voltage level of the boost voltage when the RAS signal is at a high potential and the voltage pre-charging transistor is used to push voltage level of the boost voltage when the RAS signal is at a low potential.
8. The DRAM circuit of claim 6 , wherein the even sub-word line and the odd sub-word line are each coupled to at least one memory cell.
9. A sub-word line driver for a dynamic random access memory (DRAM), comprising: a first relay transistor and a second relay transistor, wherein the source/drain terminals of the first relay transistor are connected to a main word line and an even sub-word line, the gate terminal of the first relay transistor is connected to an odd sub-word line, the source/drain terminals of the second relay transistor are connected to the main word line and the odd sub-word line, and the gate terminal of the second relay transistor is connected to the even sub-word line; a first pull-down transistor and a second pull-down transistor, wherein the source/drain terminals of the first pull-down transistor are connected to the even sub-word line and a reference voltage point, the gate terminal of the first pull-down transistor is connected to a terminal for receiving an even sub-word-line signal, the source/drain terminals of the second pull-down transistor are connected to the odd sub-word line and the reference voltage point, and the gate terminal of the second pull-down transistor is connected to a terminal for receiving an odd sub-word-line signal; and a first pass transistor and a second pass transistor, wherein the source/drain terminals of the first pass transistor are connected to the main word line and the even sub-word line, the gate terminal of the first pass transistor is connected to the terminal for receiving the odd sub-word-line signal, the source/drain terminals of the second pass transistor are connected to the main word line and the odd sub-word line, and the gate terminal of the second pass transistor is connected to the terminal for receiving the even sub-word-line signal.
10. The sub-word line driver of claim 9 , wherein the even sub-word-line signal and the odd sub-word-line signal are derived from the least significant bit of the memory address to be read.
11. The sub-word line driver of claim 9 , wherein the even sub-word line and the odd sub-word line are each coupled to at least one memory cell.
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February 14, 2001
July 16, 2002
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