A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal is established for receiving single-ended data.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A communication system comprising: a first integrated circuit configured to transmit data and a periodic signal; a bus coupled to the first integrated circuit, the bus having at least one differential interconnect line coupled to carry the periodic signal, and a single-ended interconnect line coupled to carry data; and a second integrated circuit coupled to the bus and configured to receive the data and the periodic signal, the second integrated circuit having a differential buffer coupled to receive the periodic signal and to extract a reference signal from the periodic signal, and a data buffer coupled to receive the data and the reference signal.
2. The communication system of claim 1 wherein the differential buffer is configured to extract a DC value of the periodic signal as the reference signal.
3. The communication system of claim 1 wherein the data buffer comprises compare circuitry for comparing a signal level of the data to a level of the reference signal.
4. The communication system of claim 1 wherein the first integrated circuit comprises transmitter circuitry and the second integrated circuit comprises receiver circuitry.
5. The communication system of claim 4 wherein the periodic signal is a clock signal, and wherein the second integrated circuit further comprises a clock differential buffer coupled to receive the clock signal and configured to generate an internal clock signal.
6. The communication system of claim 1 wherein the differential buffer comprises: a differential input stage having differential input transistors coupled to receive the periodic signal, and an output; a filter coupled to the output of the differential input stage; and an output stage coupled to the filter and configured to generate the reference signal at an output terminal.
7. The communication system of claim 6 wherein the differential input stage comprises a pair of input transistor having a common source terminal coupled to a current-source transistor and drain terminal respectively coupled to a pair of load transistors.
8. The communication system of claim 7 wherein the filter comprises: a resistor coupled between the output of the differential input stage and an input of the output stage; and a capacitor coupled between the input of the output stage and ground.
9. The communication system of claim 1 wherein the data buffer comprises: an input stage coupled to receive the data at an input and to regenerate the data at an output; and a compare circuit having a first input coupled to the output of the input stage, a second input coupled to the reference signal, and an output.
10. A method of communicating data comprising: transmitting a differential periodic signal over differential lines in a communication bus; transmitting single-ended data over single-ended lines in the communication bus; extracting a reference signal for the single-ended data from the differential periodic signal; receiving the single-ended data at an input buffer; and comparing a level of the single-ended data with a level of the reference signal.
11. An integrated circuit comprising: a differential buffer coupled to receive a differential periodic signal and to extract a DC reference signal from the differential periodic signal; and a data buffer coupled to receive a single-ended data and the reference signal, the data buffer being configured to determine a logic level of the single-ended data by comparing it to the reference signal.
12. The integrated circuit of claim 11 wherein the differential periodic signal is a differential clock signal having a duty cycle of approximately 50%.
13. The integrated circuit of claim 12 further comprising a differential clock buffer coupled to receive the differential clock signal and the reference signal.
14. A communication system comprising: a first integrated circuit configured to transmit data and a periodic signal; a bus coupled to the first integrated circuit and coupled to carry the periodic signal and data on respective interconnect lines; and a second integrated circuit coupled to the bus and configured to receive the data and the periodic signal, the second integrated circuit including: a reference buffer coupled to receive the periodic signal and configured to extract a DC level of the periodic signal to be used as a reference signal, and a data buffer having a first input coupled to receive the data and a second input coupled to receive the reference signal, the data buffer being configured to determine a binary logic state of the data by comparing a level of the data to the reference signal.
15. The communication system of claim 14 wherein the periodic signal is a differential signal, and the reference buffer is a differential buffer.
16. The communication system of claim 15 wherein the reference buffer comprises: an input differential stage coupled to receive the differential periodic signal; a low pass filter coupled to an output of the input differential stage; and an output buffer having an input coupled to an output of the filter, and an output coupled to generate the reference signal.
17. The communication system of claim 16 wherein the filter comprises a resistor coupled to a capacitor.
18. The communication system of claim 17 wherein the output buffer comprises a differential stage having a first input coupled to the output of the filter and a second input coupled to the output of the output buffer carrying the reference signal.
19. The communication system of claim 15 further comprising a differential clock buffer having a pair of inputs coupled to receive the differential periodic signal, a reference input coupled to receive the reference signal and an output.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 27, 2000
July 23, 2002
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