Banks are arranged on a memory chip, forming a matrix. A data input/output circuit is provided at one side of the memory chip. A data bus is provided among the banks and connected to the data input/output circuit. Each bank has a plurality of memory cell arrays a cell-array controller, a row decoder, column decoders, and a DQ buffer. The cell-array controller and the row decoder oppose each other. The column decoders oppose the DQ buffer. Local DQ lines are provided between the memory cell arrays, and global DQ liens extend over the memory cell arrays. The local DQ lines extend at right angles to the global DQ lines.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A test circuit for testing a semiconductor memory comprising a memory cell array having first and second memory cell blocks, comprising: a register which holds first and second test data; a data-writing circuit which simultaneously writes the first test data to a first memory cell in said first memory cell block and the second test data to a second memory cell in said second memory cell block; a data-reading circuit which simultaneously reads first read data stored in said first memory cell and second read data stored in said second memory cell; a comparing circuit which compares the first read data with the first test data and outputs first output data, and which compares the second read data with the second test data and outputs second output data; and a determining circuit which determines whether the first and second memory cells are flawless based on the first and second output data, and said determining circuit outputs one-bit data which shows defective when at least one of the first and second output data shows that the at least one of the first and second memory cells is defective, wherein said determining circuit outputs a first signal which shows whether the first memory cell is flawless and a second signal which shows whether the second memory cell is flawless, when at least one of the first and second output data shows that the at least one of the first one of the first and second memory cells is defective.
2. The test circuit according to claim 1 further comprising a first latch circuit latching the first signal and a second latch circuit latching the second signal, wherein the first and second signals output sequentially.
3. A test circuit for testing a semiconductor memory comprising a memory cell array having a plurality of memory cell blocks, comprising: a register which holds a plurality of test data; a data-writing circuit which simultaneously writes the test data to memory cells in said memory cell blocks, a data-reading circuit which simultaneously reads a plurality of read data stored in said memory cells; a comparing circuit which compares the read data with the test data and outputs a plurality of output data, and a determining circuit which determines whether the memory cells are flawless based on the output data, and said determining circuit outputs one-bit data which shows that the memory cells are defective when at least one of the output data shows that the at least one of the memory cells is defective, wherein said determining circuit output signals which show whether at least one of the memory cells is flawless, when at least one of the output data shows that the at least one of the memory cells is defective.
4. The test circuit according to claim 3 further comprising latch circuits latching the signals, wherein the signals are output sequentially.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 21, 2001
July 30, 2002
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