On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor integrated circuit device comprising: a first semiconductor region including a first wiring layer having a first thickness, a second wiring layer having a second thickness and a third wiring layer having a third thickness; and a second semiconductor region including a fourth wiring layer having the first thickness, a fifth wiring layer having the second thickness and a sixth wiring layer having the third thickness.
2. A semiconductor integrated circuit device comprising: a first semiconductor region including a plurality of wiring layers having predetermined thickness respectively; and a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region, wherein the uppermost wiring layer in the second semiconductor region includes power supply line.
3. A semiconductor integrated circuit device comprising: a first semiconductor region including a plurality of wiring layers having predetermined thicknesses respectively; and a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region, wherein the uppermost wiring layer in the second semiconductor region includes critical path signal line.
4. A semiconductor integrated circuit device comprising: a first semiconductor region including a plurality of wiring layers having predetermined thicknesses respectively; and a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region, wherein the thicknesses of the upper most wiring layer in the second region is thickest in the wiring layers.
5. A semiconductor integrated circuit device comprising: a first semiconductor region including a plurality of wiring layers having predetermined thicknesses respectively; and a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region, wherein the uppermost wiring layer in the second semiconductor region has width wider than the width of other wiring layers.
6. A semiconductor integrated circuit device comprising: a first semiconductor region including three wiring layers having predetermined thickness respectively, a first plug connected between upper most wiring layer and a medium wiring layer and a second plug connected between the medium wiring layer and lower wiring layer; and a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region; wherein the first plug is wider in horizontal direction than the second plug.
7. A semiconductor integrated circuit device comprising: a first semiconductor region including a plurality of wiring layers having predetermined thicknesses respectively; and a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region and an interconnection wiring layer coupled to an upper most wiring layer in the first semiconductor region and an upper most wiring layer in the second semiconductor region.
8. A semiconductor integrated circuit device comprising: a first semiconductor region including a first wiring layer having a first pattern, a first insulating layer provided below the first wiring layer, a second wiring layer having the second pattern identical to the first pattern and provided below the first insulating layer, a second insulating layer provided below the second wiring layer, and a third wiring layer having a third pattern and provided below the second insulating layer; and a second semiconductor region including a fourth wiring layer having a fourth pattern, a third insulating layer provided below the fourth wiring layer, a fifth wiring layer having a fifth pattern and provided below the third insulating layer, a fourth insulating layer provided below the fifth wiring layer, and a sixth wiring layer having a sixth pattern and provided below the fourth insulating layer.
9. A semiconductor integrated circuit device comprising: a first semiconductor region including a first wiring layer having a first thickness, a second wiring layer having a second thickness and provided below the first wiring layer, and a third wiring layer having a third thickness and provided below the second wiring layer; and a second semiconductor region including a fourth wiring layer having the fourth thickness, a fifth wiring layer having the fifth thickness and provided below the fourth wiring layer, and a sixth wiring layer having the sixth thickness and provided below the fifth wiring layer; wherein the first thickness and the fourth thickness is substantially same.
10. A semiconductor integrated circuit device comprising: a first semiconductor region including a first wiring layer having a first pattern, a first insulating layer provided below the first wiring layer, a second wiring layer having the second pattern and provided below the first insulating layer, a second insulating layer provided below the second wiring layer, and a third wiring layer having a third pattern identical to the first pattern and provided below the second insulating layer; and a second semiconductor region including a fourth wiring layer having a fourth pattern, a third insulating layer provided below the fourth wiring layer, a fifth wiring layer having a fifth pattern and provided below the third insulating layer, a fourth insulating layer provided below the fifth wiring layer, and sixth wiring layer having a sixth pattern and provided below the fourth insulating layer.
11. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including a first wiring layer having a first thickness, a second wiring layer having a second thickness and a third wiring layer having a third thickness, the macro cell comprising: a second semiconductor region including a fourth wiring layer having the first thickness, a fifth wiring layer having the second thickness and a sixth wiring layer having the third thickness.
12. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including a plurality of wiring layers having predetermined thickness respectively, the macro cell comprising: a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region, wherein the uppermost wiring layer in the second semiconductor region includes power supply line.
13. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including a plurality of wiring layers having predetermined thicknesses respectively, the macro cell comprising: a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region, wherein the uppermost wiring layer in the second semiconductor region includes critical path signal line.
14. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including a plurality of wiring layers having predetermined thicknesses respectively, the macro cell comprising: a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region, wherein the thickness of the upper most wiring layer in the second region is thickest in the wiring layers.
15. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including a plurality of wiring layers having predetermined thicknesses respectively, the macro cell comprising: a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region, wherein the uppermost wiring layer in the second semiconductor region has width wider than the width of other wiring layers.
16. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including three wiring layers having predetermined thickness respectively, a first plug connected between upper most wiring layer and a medium wiring layer and a second plug connected between the medium wiring layer and lower wiring layer, the macro cell comprising: a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region; wherein the first plug is wider in horizontal direction than the second plug.
17. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including a plurality of wiring layers having predetermined thicknesses respectively, the macro cell comprising: a second semiconductor region including same number of wiring layers as the wiring layers in the first semiconductor region and an interconnection wiring layer coupled to an upper most wiring layer in the first semiconductor region and an upper most wiring layer in the second semiconductor region.
18. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including a first wiring layer having a first pattern, a first insulating layer provided below the first wiring layer, a second wiring layer having the second pattern identical to the first pattern and provided below the first insulating layer, a second insulating layer provided below the second wiring layer, and a third wiring layer having a third pattern and provided below the second insulating layer, the macro cell comprising: a second semiconductor region including a fourth wiring layer having a fourth pattern, a third insulating layer provided below the fourth wiring layer, a fifth wiring layer having a fifth pattern and provided below the third insulating layer, a fourth insulating layer provided below the fifth wiring layer, and a sixth wiring layer having a sixth pattern and provided below the fourth insulating layer.
19. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including a first wiring layer having a first thickness, a second wiring layer having a second thickness and provided below the first wiring layer, and third wiring layer having a third thickness and provided below the second wiring layer, the macro cell comprising: a second semiconductor region including a fourth wiring layer having the fourth thickness, a fifth wiring layer having the fifth thickness and provided below the fourth wiring layer, and a sixth wiring layer having the sixth thickness and provided below the fifth wiring layer; wherein the first thickness and the fourth thickness is substantially same.
20. A semiconductor integrated circuit device which comprises a macro cell and a first semiconductor region including a first wiring layer having a first pattern, a first insulating layer provided below the first wiring layer, a second wiring layer the second pattern and provided below the first insulating layer, a second insulating layer provided below the second wiring layer, and a third wiring layer having a third pattern identical to the first pattern and provided below the second insulating layer, the macro cell comprising: a second semiconductor region including a fourth wiring layer having a fourth pattern, a third insulating layer provided below the fourth wiring layer, a fifth wiring layer having a fifth pattern and provided below the third insulating layer, a fourth insulating layer provided below the fifth wiring layer, and sixth wiring layer having a sixth pattern and provided below the fourth insulating layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 21, 2000
August 6, 2002
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