A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming metal interconnects in a semiconductor structure comprising the steps of: providing a semiconductor structure having an interconnect opening having sidewalls and a bottom formed therein, depositing a seed layer of a first metal having an average grain size of not larger than 0.5 m, heating said semiconductor structure to a temperature sufficient to grow said average grain size of said seed layer to at least 1.5 times of said average grain size, and depositing a filler layer of a second metal in said interconnect opening overlaying said seed layer such that said filler layer of said second metal has an average grain size within 20% of said average grain size of said seed layer.
2. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the step of depositing said filler layer of a second metal that is the same as the first metal in the seed layer.
3. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the step of depositing said filler layer and said seed layer in Cu.
4. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the steps of depositing said filler layer in Au and depositing said seed layer in Au or Pt.
5. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the steps of depositing said filler layer in Cu and depositing said seed layer in Pt.
6. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the step of depositing said filler layer in Ni and depositing said seed layer in Ni.
7. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the step of heating said seed layer to a temperature between about 50 C. and about 500 C.
8. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the step of heating said seed layer to a temperature between about 300 C. and about 400 C. when said first metal is Cu.
9. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the step of heating said seed layer to a temperature between about 50 C. and about 500 C. in a reducing atmosphere of forming gas or N 2 or an inert gas, He or Ar.
10. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the step of heating said seed layer for a time period of less than 2 hrs.
11. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the step of heating said seed layer for a time period between about 30 min and about 2 hrs when said first metal is Cu.
12. A method for forming metal interconnects in a semiconductor structure according to claim 1 further comprising the step of depositing said seed layer to a thickness between about 0.0005 m and about 0.50 m.
13. A semiconductor structure comprising: an insulating material layer on a top surface of the semiconductor structure, an interconnect opening having sidewalls and a bottom in said insulating material layer, a seed layer of a first metal on top of a diffusion barrier layer, said seed layer being formed of grains having an average grain size not smaller than 0.005 m, and a filler layer of a second metal filling said interconnect opening formed of grains having an average grain size with a range of 20% of the average grain size of said seed layer.
14. A semiconductor structure according to claim 13 , wherein said seed layer being formed of grains having an average grain size not smaller than 0.05 m.
15. A semiconductor structure according to claim 13 , wherein said average grain size of said seed layer is not larger than 0.2 m.
16. A semiconductor structure according to claim 13 , wherein said first metal and said second metal are of the same material.
17. A semiconductor structure according to claim 13 , wherein said first metal and said second metal are both Cu.
18. A semiconductor structure according to claim 13 , wherein said first metal is Au or Pt, said second metal is Au.
19. A semiconductor structure according to claim 13 , wherein said first metal is Pt, said second metal is Cu.
20. A semiconductor structure according to claim 13 , wherein said first metal is Ni, said second metal is Ni.
21. A semiconductor structure according to claim 13 , wherein said seed layer having a thickness between about 0.0005 m and about 0.5 m.
22. A semiconductor structure according to claim 13 , wherein said seed layer preferably having a thickness between about 0.0005 m and about 0.2 m.
23. A semiconductor structure according to claim 13 , wherein said seed layer more preferably having a thickness between about 0.0005 m and about 0.05 m.
24. A method for forming metal interconnect in a semiconductor structure comprising the steps of: providing a semiconductor structure having an interconnect opening having sidewalls and a bottom formed therein, depositing a seed layer of a first metal having a thickness of at least 0.05 m in said interconnect opening, removing a layer of said first metal from a top surface of said seed layer that is at least 20% the thickness of said seed layer, and depositing a filler layer of a second-metal in said interconnect opening overlaying said remaining seed layer such that ax said filler layer of said second metal has an average grain size larger than 0.005 m.
25. A method for forming metal interconnect in a semiconductor structure according to claim 24 further comprising the step of depositing a diffusion barrier layer in said interconnect opening prior to said deposition step for said seed layer.
26. A method for forming metal interconnect in a semiconductor structure according to claim 24 further comprising the step of depositing said seed layer and said filler layer of the same metal.
27. A method for forming metal interconnect in a semiconductor structure according to claim 24 further comprising the step of depositing said seed layer and said filler layer of Cu.
28. A method for forming metal interconnect in a semiconductor structure according to claim 24 further comprising the step of depositing said seed layer of Cu to a thickness of at least 0.05 m.
29. A method for forming metal interconnect in a semiconductor structure according to claim 24 further comprising the step of depositing said seed layer of Cu to a thickness of at least 0.05 m such that said filler layer subsequently deposited has an average grain size within 20% of said average grain size of said seed layer.
30. A method for forming metal interconnect in a semiconductor structure according to claim 24 further comprising the step of depositing said seed layer of Cu to a thickness between about 0.05 m and about 0.5 m.
31. A method for forming metal interconnect in a semiconductor structure according to claim 24 further comprising the step of depositing said seed layer of Cu to a thickness preferably between about 0.10 m and about 0.50 m.
32. A method for forming metal interconnect in a semiconductor structure according to claim 24 further comprising the step of depositing said seed layer of Cu to a thickness between about 0.05 m and about 0.50 m such that a subsequently deposited filler layer has an average grain size that is equal to or larger than the thickness of the seed layer after a layer of Cu is removed from a top surface of said seed layer.
33. A method for forming metal interconnect in a semiconductor structure according to claim 24 further comprising the step of annealing said seed layer formed of said first metal at an annealing temperature to increase the grain size of said first metal prior to said removal step.
34. A method for forming metal interconnect in a semiconductor structure according to claim 24 , wherein said step of removing a layer of the first metal from a top surface of the seed layer is carried out by a technique selected from the group consisting of electro-etching, ion beam sputtering, reactive ion etching and chemical mechanical polishing.
35. A method for forming metal interconnect in a semiconductor structure according to claim 24 , wherein said seed layer of said first metal is deposited by a technique selected from the group consisting of physical vapor deposition, evaporation, ionized physical vapor deposition, chemical vapor deposition, electroless plating and electrodeposition.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 4, 2001
August 6, 2002
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