A method for fabricating an integrated circuit chip includes the steps of:(a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of the circuit board unit;(b) forming a die having an upper surface provided with a plurality of solder pads;(c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed;(d) wire-bonding the solder pads to the contact pads via conductive wires;(e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit chip comprising: a circuit board unit having a bottom surface formed with a die-receiving cavity, a top surface formed with a bore to access said die-receiving cavity and further formed with a plurality of contact pads, and opposite side portions formed with a plurality of positioning notches that correspond respectively to said contact pads; a die having an upper surface provided with a plurality of solder pads, said die being placed in said die-receiving cavity such that said solder pads are exposed via said bore in said circuit board unit; a plurality of conductive wires that extend through said bore and that wire-bond said solder pads to said contact pads; a lead frame having a plurality of leads, one end of each of said leads being inserted into a respective one of said positioning notches; a conductive contact layer to bond said leads on said lead frame onto corresponding ones of said contact pads adjacent to said side portions of said circuit board unit; and a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
2. The integrated circuit chip of claim 1 , wherein said conductive contact layer is formed from a silver epoxy.
3. The integrated circuit chip of claim 1 , wherein said conductive contact layer is formed from solder paste.
4. An integrated circuit chip comprising: a circuit board unit having a top surface formed with a die-receiving cavity and a plurality of contact pads, and opposite side portions formed with a plurality of positioning notches that correspond respectively to said contact pads; a die having an upper surface provided with a plurality of solder pads, said die being placed in said die-receiving cavity such that said solder pads on said die are exposed from said die-receiving cavity; a plurality of conductive wires that wire-bond said solder pads to said contact pads; a lead frame having a plurality of leads, one end of each of said leads being inserted into a respective one of said positioning notches; a conductive contact layer to bond said leads on said lead frame onto corresponding ones of said contact pads adjacent to said opposite side portions of said circuit board unit; and a plastic protective layer to encapsulate said circuit board unit and at least a portion of said lead frame.
5. The integrated circuit chip of claim 4 , wherein said conductive contact layer is formed from a silver epoxy.
6. The integrated circuit chip of claim 4 , wherein said conductive contact layer is formed from solder paste.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 22, 2001
August 6, 2002
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