Three stage router for broadcast application

1. A signal router having M input terminals and N output terminals and comprising: an input router stage having M inputs connected respectively to the M input terminals of the router and composed of M/m router modules each having m inputs, p outputs and a first switch means for selectively connecting any one of the m inputs to any one of the p outputs, and an intermediate router stage composed of p router modules each having M/m inputs and N/n outputs and a second switch means for selectively connecting any one of the M/m inputs to any one of the N/n outputs, an output router stage composed of N/n router modules each having p inputs and n outputs and a third switch means for selectively connecting any one of the p inputs to any one of the n outputs, p*(M/m) input stage clocked storage elements connected respectively between the outputs of the router modules of the input router stage and the inputs of the router modules of the intermediate router stage, the input stage clocked storage elements being responsive to a trigger event of a clock signal to capture a signal level present at the ith output of the jth router module of the input router stage (1< i< p; 1< j< M/m) and hold the signal level at the jth input of the pth router module of the intermediate router stage until a subsequent trigger event of the clock signal, p*N/n intermediate stage clocked storage elements connected respectively between the outputs of the router modules of the intermediate router stage and the inputs of the router modules of the output router stage, the intermediate stage clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the kth output of the lth router module of the second router stage (1< k< N/n; 1< 1< p) and hold the signal level at the lth input of the kth router module of the output router stage until a subsequent trigger event of the clock signal, and N output stage clocked storage elements connected respectively between the outputs of the router modules of the third router stage and the output terminals of the router, the output stage clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the uth output of the vth router module of the third router stage (1< u< n; 1< v< N/n) and hold the signal level at the (n*v u)th output terminal of the router until a subsequent trigger event of the clock signal.

2. A signal router according to claim 1 , wherein the switch means of each router module of at least one stage is operable for selectively connecting any one of the inputs of the module to any selected set of outputs of the module.

3. A signal router according to claim 1 , wherein the first switch means is operable for selectively connecting any one of the m inputs of a router module of the input stage to any selected set of the p outputs thereof, the second switch means is operable for selectively connecting any one of the M/m inputs of a router module of the intermediate stage to any one of the N/n outputs thereof, and the third switch means is operable for selectively connecting any one of the p inputs of a router module of the output stage to any one of the n outputs thereof.

4. A signal router comprising: a first router stage composed of M/m router modules each having m inputs and m n outputs and a first switch means for selectively connecting any one of the m inputs to any selected set of the m n outputs, a second router stage composed of m n router modules each having M/m inputs and N/n outputs and a second switch means for selectively connecting one of the M/m inputs to any selected set of the N/n outputs, a third router stage composed of N/n router modules each having m n inputs and n outputs and a third switch means for selectively connecting any one of the m n inputs to any selected set of the n outputs, (n m)*(M/m) first clocked storage elements connected respectively between the outputs of the router modules of the first router stage and the inputs of the router modules of the second router stage, the first clocked storage elements being responsive to a trigger event of a clock signal to capture a signal level present at the ith output of the jth router module of the first router stage (1< i< m; 1< j< M/m) and hold the signal level at the jth input of the ith router module of the second router stage until a subsequent trigger event of said clock signal, (n m)*(N/n) second clocked storage elements connected respectively between the outputs of the router modules of the second router stage and the inputs of the router modules of the third router stage, the second clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the kth output of the lth router module of the second router stage (1< k< N/n; 1< 1< m n) and hold the signal level at the lth input of the kth router module of the third router stage until a subsequent trigger event of said clock signal, and N third clocked storage elements connected respectively between the outputs of the router modules of the third router stage and the output terminals of the router, the third clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the uth output of the vth router module of the third router stage (1< u< n; 1< v< N/n) and hold the signal level at the (v*n u)th output terminal of the router until a subsequent trigger event of said clock signal.

5. A signal router comprising: a first router stage composed of M/m router modules each having m inputs and p outputs and a first switch means for selectively connecting any one of the m inputs to any selected set of the p outputs, a second router stage having p*M/m inputs associated respectively with the outputs of the router modules of the first router stage and also having q*N/n outputs and including a second switch means for selectively interconnecting the p*M/m inputs and the q*N/n outputs, a third router stage composed of N/n router modules each having p inputs and n outputs and a third switch means for selectively connecting any one of the p inputs to any selected set of the n outputs, the inputs of the router modules of the third router stage being associated respectively with the q*N/n outputs of the second router stage, p*(M/m) first clocked storage elements connected respectively between the outputs of the router modules of the first router stage and the respectively associated inputs of the second router stage, the first clocked storage elements being responsive to a trigger event of a clock signal to capture a signal level present at the ith output of the jth router module of the first router stage (1< i< m; 1< j< M/m) and hold the signal level at the associated input of the second router stage until a subsequent trigger event of the clock signal, p*(N/n) second clocked storage elements connected respectively between the outputs of the second router stage and the respectively associated inputs of the router modules of the third router stage, the second clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at an output of the second router stage and hold the signal level at the associated input of a router module of the third router stage until a subsequent trigger event of the clock signal, and N third clocked storage elements connected respectively between the outputs of the router modules of the third router stage and the output terminals of the router, the third clocked storage elements being responsive to a trigger event of said clock signal to capture a signal level present at the uth output of the vth router module of the first router stage (1< u< n; 1< v< N/n) and hold the signal level at the (n*v u)th output terminal of the router until a subsequent trigger event of the clock signal.