Loadless NMOS four transistor SRAM cell

1. A semiconductor memory cell device comprising: a word line for receiving an activation signal; a first access transistor and a second access transistor for processing the activation signal from the word line; a first drive transistor and a second drive transistor for storing a bit value, the first access transistor cross-coupled to the second drive transistor and the second access transistor cross-couple to the first drive transistor; and a bit line and a complimentary N-bit line for transmitting the bit value during input or output operations; where the first access transistor, the second access transistor, the first drive transistor, and the second drive transistor being NMOS transistors, the semiconductor memory cell device maintains a stable data hold by utilizing a sub-threshold voltage to charge the word line, the sub-threshold voltage being higher than the low voltage reference of the memory cell device and lower than the threshold voltage of the first access transistor or the second access transistor, the application of the sub-threshold voltage occurring during non-active and non-charging operations of the memory cell device.

2. The semiconductor memory cell device of claim 1 , wherein the memory cell does not require any load elements.

3. The semiconductor memory cell device of claim 1 , wherein the sub-threshold voltage biased word line require a shorter active time compared to the precharge time.